Abstract: An approach is provided in which the approach builds a combination model that includes a normal status model and an abnormal status model. The normal status model is built from a set of time-sequenced normal status records and the abnormal status model is built from a set of time-sequenced abnormal status records. The approach computes a set of time-sequenced coefficient combination values of the normal status model and the abnormal status model based on applying a set of fitting coefficient characteristics to the normal status model and the abnormal status model. The approach performs goal seek analysis on a system using the combination model and the set of time-sequenced coefficient combination values.

Abstract: An optical ferrule assembly includes a hybrid optical ferrule having a glass portion assembled to a polymeric portion. The polymeric portion includes a groove for receiving and supporting an optical fiber having opposing open front and back ends. A light redirecting member includes an input surface for receiving light from the optical fiber and a light redirecting side. The open back end of the groove and the input surface define a recessed region therebetween. The glass portion includes an optically transparent glass insert disposed in the recessed region conforming in shape to an internal shape of the recessed region. An optical fiber is received and supported in the groove. The optical fiber includes a fiber end laser welded to the glass insert so that a central light ray from the optical fiber propagates through the glass insert before being received and redirected by the light redirecting side.

Abstract: Control systems are provided that provide thermodynamically decoupled control of temperature and relative humidity and/or reduce or prevent frost formation or remove previously-formed frost. The control systems herein may be included as a component of a heating, ventilation, air conditioning, and refrigeration system that includes a heat exchanger.

Abstract: Control systems are provided that provide thermodynamically decoupled control of temperature and relative humidity and/or reduce or prevent frost formation or remove previously-formed frost. The control systems herein may be included as a component of a heating, ventilation, air conditioning, and refrigeration system that includes a heat exchanger.

Abstract: Control systems are provided that provide thermodynamically decoupled control of temperature and relative humidity and/or reduce or prevent frost formation or remove previously-formed frost. The control systems herein may be included as a component of a heating, ventilation, air conditioning, and refrigeration system that includes a heat exchanger.

Abstract: Control systems are provided that provide thermodynamically decoupled control of temperature and relative humidity and/or reduce or prevent frost formation or remove previously-formed frost. The control systems herein may be included as a component of a heating, ventilation, air conditioning, and refrigeration system that includes a heat exchanger.

Abstract: Cylindrical screens and screen assemblies for use with perforated base pipe or casing for sand control in wellbores have generally longitudinally extending slots punched in the screen. The outer surface of the screen material is deformed below the inner surface causing apertures to form along the longitudinal edges of the slot. The slots are generally longitudinally aligned with the longitudinal axis of the cylindrical screens whether butt-welded or spiral-rolled and welded by determining the angle at which the slots need to be punched to result in such alignment. End caps which connect between the screen and the casing extend over the ends of the cylindrical screen and are welded thereto to minimize sand entry. At least one of the end caps may include an expansion joint to permit relative expansion and contraction between the screen and the casing particularly when used in thermal recovery operations.

Abstract: Systems and methods are provided for modulating light of a wavelength of interest. The modulator assembly includes a plasmonic layer that supports surface plasmon polaritons at the wavelength of interest and a layer of solid-state phase change material having a first phase in which it is substantially transparent to light of the wavelength of interest and a second phase in which it is substantially opaque to light of the wavelength of interest. A control mechanism is configured to alter the phase of the solid-state phase change material between the first phase and the second phase. Each of the plasmonic layer and the layer of solid-state phase change material are configured as to provide a plasmonic mode of transmission for light of the wavelength of interest.

Abstract: Systems and methods are provided for modulating light of a wavelength of interest. The modulator assembly includes a plasmonic layer that supports surface plasmon polaritons at the wavelength of interest and a layer of solid-state phase change material having a first phase in which it is substantially transparent to light of the wavelength of interest and a second phase in which it is substantially opaque to light of the wavelength of interest. A control mechanism is configured to alter the phase of the solid-state phase change material between the first phase and the second phase. Each of the plasmonic layer and the layer of solid-state phase change material are configured as to provide a plasmonic mode of transmission for light of the wavelength of interest.

Abstract: A memory circuit includes a first memory array, a second memory array and a switch module, wherein the first memory array has a first node and a second node, the second memory array has a third node and a fourth node, the first node is coupled to a first supply voltage, and the fourth supply voltage is coupled to a second supply voltage smaller than the first supply voltage. The switch module is coupled to the second node, the third node, the first supply voltage and the second supply voltage. When the memory circuit is operated under an inactive mode, the switch module electrically connects the second node to the third node, electrically disconnects the second node from the second supply voltage, and electrically disconnects the third node from the first supply voltage.

Abstract: A memory circuit includes a first memory array, a second memory array and a switch module, wherein the first memory array has a first node and a second node, the second memory array has a third node and a fourth node, the first node is coupled to a first supply voltage, and the fourth supply voltage is coupled to a second supply voltage smaller than the first supply voltage. The switch module is coupled to the second node, the third node, the first supply voltage and the second supply voltage. When the memory circuit is operated under an inactive mode, the switch module electrically connects the second node to the third node, electrically disconnects the second node from the second supply voltage, and electrically disconnects the third node from the first supply voltage.

Abstract: A method and system for modeling uncertainties in integrated circuits, systems and fabrication processes may include defining interval values for each uncertain component or parameter in a circuit or system. The method may also include replacing scalar operations with interval operations in an algorithm and discontinuing interval operations in the algorithm in response to a predetermined condition. The method may also include generating a plurality of scalar samples from a plurality of intervals and determine a distribution of each uncertain component or parameter from the scalar samples of the intervals.

Abstract: Methods and apparatus implementing techniques for prevention of metastability in a bistable circuit. The techniques include detecting a change in a data signal, sampling the detected change in reference to a sampling window of a clock signal input of a bistable circuit to determine if the detected change occurs within the sampling window, and selecting a stable data input to present to an input of the bistable circuit based on whether the detected change occurs within the sampling window. The sampling window represents a time period during which a change in the data signal can cause metastability in a bistable circuit.

Abstract: A method and circuit for transferring multiple bits of data across asynchronous clock domains is provided. The method includes detecting a change in a status bit of a data word being transferred from a source in a source clock domain to a destination register in a destination clock domain, the source clock and destination clock being asynchronous. The method includes sampling the detected change in reference to a change window where the change window is sized to encompass all bits of the data word. A stable input is selected for each bistable circuit of the destination register based on whether the detected change in the status bit is likely to produce metastability in the receiving register.

Abstract: A method and circuit for transferring multiple bits of data across asynchronous clock domains is provided. The method includes detecting a change in a status bit of a data word being transferred from a source in a source clock domain to a destination register in a destination clock domain, the source clock and destination clock being asynchronous. The method includes sampling the detected change in reference to a change window where the change window is sized to encompass all bits of the data word. A stable input is selected for each bistable circuit of the destination register based on whether the detected change in the status bit is likely to produce metastability in the receiving register.

Abstract: Methods and apparatus implementing techniques for prevention of metastability in a bistable circuit. The techniques include detecting a change in a data signal, sampling the detected change in reference to a sampling window of a clock signal input of a bistable circuit to determine if the detected change occurs within the sampling window, and selecting a stable data input to present to an input of the bistable circuit based on whether the detected change occurs within the sampling window. The sampling window represents a time period during which a change in the data signal can cause metastability in a bistable circuit.

Abstract: A circuit and method for generating a write enable pulse that is independent of the clock duty cycle and the clock frequency. The circuit includes a pulse generator for generating a pulse in response to a clock signal and a write enable signal generator for generating a write enable pulse. The pulse tracks the leading edge of the clock signal. A logic circuit is coupled to the pulse generator and the write enable signal generator to generate the write enable pulse by combining the pulse and the write enable signal.

Abstract: A digital crossbar switch utilizes an asynchronous RAM to provide high density and low latency storage and a write enable pulse generator to generate write enable pulses that are independent of the clock signal duty cycles. The crossbar switch includes a plurality of ports coupled to a bus, at least one memory element coupled to one of the plurality of ports, and a circuit for generating a write enable pulse coupled to each of the memory element. The circuit for generating the write enable pulse includes a pulse generator for generating a pulse, the pulse tracking a leading edge of a clock signal, a write enable signal generator for generating a write enable signal, and a first logic circuit coupled to the pulse generator and the write enable signal generator for generating the write enable pulse by combining the pulse and the write enable signal.