Patents by Inventor James MacArthur

James MacArthur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11815881
    Abstract: Mechanisms can be designed to manage non-contact forces to reduce energy consumption and/or to control interactions between the parts. Management of non-contact forces is especially useful in micro-scale and nano-scale mechanisms, where van der Waals attraction between parts of the mechanism may be significant to the operation of the mechanism.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: November 14, 2023
    Assignee: CBN Nano Technologies Inc.
    Inventors: James F. Ryley, Mark N. Jobes, James MacArthur, Jeffrey E. Semprebon
  • Publication number: 20230296163
    Abstract: A selective motion transfer mechanism acts to transmit rotary motion between a common element and a selected one of multiple channel elements. The common element can be positioned in alignment with any one of the channel elements, and when so aligned, rotation of one of the aligned elements causes rotation of the other.
    Type: Application
    Filed: March 21, 2022
    Publication date: September 21, 2023
    Inventors: James MacArthur, Robert A. Freitas, Jr., James F. Ryley, III
  • Patent number: 11720084
    Abstract: Logic mechanisms operate to define the position of at least one mechanical output based on the position of at least one mechanical input. Some mechanisms are configured to determine, based on the input position(s), whether a path to transmit motion to an output exists or does not exist. Some mechanisms are configured to determine, based on the input position(s), whether or not motion of a driven element can be accommodated without moving an output. Some mechanisms are configured to determine, based on the input position(s), whether or not one or more elements are constrained to transmit motion to an output.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: August 8, 2023
    Assignee: CBN Nano Technologies Inc.
    Inventors: James F. Ryley, III, Mark N. Jobes, James MacArthur, Jeffrey E. Semprebon
  • Publication number: 20230238965
    Abstract: Mechanisms can be designed to manage non-contact forces to reduce energy consumption and/or to control interactions between the parts. Management of non-contact forces is especially useful in micro-scale and nano-scale mechanisms, where van der Waals attraction between parts of the mechanism may be significant to the operation of the mechanism.
    Type: Application
    Filed: September 22, 2021
    Publication date: July 27, 2023
    Inventors: James F. Ryley, III, Mark N. Jobes, James MacArthur, Jeffrey E. Semprebon
  • Publication number: 20230087289
    Abstract: Logic mechanisms operate to define the position of at least one mechanical output based on the position of at least one mechanical input. Some mechanisms are configured to determine, based on the input position(s), whether a path to transmit motion to an output exists or does not exist. Some mechanisms are configured to determine, based on the input position(s), whether or not motion of a driven element can be accommodated without moving an output. Some mechanisms are configured to determine, based on the input position(s), whether or not one or more elements are constrained to transmit motion to an output.
    Type: Application
    Filed: September 22, 2021
    Publication date: March 23, 2023
    Inventors: James F. Ryley, III, Mark N. Jobes, James MacArthur, Jeffrey E. Semprebon
  • Publication number: 20120048153
    Abstract: The invention relates to a table comprising at least three legs and a stabiliser. The stabiliser comprises a rotatable member extending outwardly from a vertical axis of the table. The table may be stabilised by locating the table on the ground such that three legs of said table contact the ground and the stabiliser is not in contact with the ground, and then rotating the rotatable member so as to cause it to come in contact with the ground.
    Type: Application
    Filed: April 13, 2010
    Publication date: March 1, 2012
    Inventor: Rohan James Macarthur-Onslow
  • Patent number: 7474121
    Abstract: A mask programmable integrated circuit includes a read only memory (ROM), a random access memory (RAM), and a controller. The controller couples to the ROM and RAM. The controller senses a reset condition and, in response, directs a clear of the RAM or a preload of contents of the ROM to the RAM. The preload can be performed after a successful self-test of the RAM is achieved. The RAM has a variable word length and depth size and can be configured to operate in one of many modes. The integrated circuit further includes a first and a second multiplexer (MUX). The first MUX is interposed between the RAM and the ROM, and selectively couples either the ROM data or the built-in self-test (BIST) data to the first MUX output. The second MUX is interposed between the first MUX and the RAM, and selectively couples either the output of the first MUX or a (synchronous or asynchronous) data input to the RAM.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: January 6, 2009
    Assignee: Altera Corporation
    Inventors: David A. Asson, James Macarthur
  • Patent number: 6347378
    Abstract: A programmable logic device having redundant sets of logic blocks which are capable of being enabled or disabled. The programmable logic device includes a plurality of sets of logic blocks, a plurality of routing resources and a programming circuit. Good logic blocks are enabled and fully operational when programmed. Nonfunctional logic blocks are disabled, powered off and invisible to the programming software. Each set of logic blocks has a corresponding routing resource. The routing resource corresponding to an enabled set of logic blocks is capable of being configured to provide input and output data paths for the enabled set of logic blocks. The routing resource corresponding to a disabled set of logic blocks is capable of being configured to bypass the disabled set of the logic blocks. The programming circuit stores the configuration data for the routing resources and is capable of providing the configuration data to a routing resource that corresponds to an enabled set of logic blocks.
    Type: Grant
    Filed: April 24, 2000
    Date of Patent: February 12, 2002
    Assignees: Quicklogic Corp., Cypress Semiconductor Corp.
    Inventors: James MacArthur, Timothy Lacey
  • Patent number: 6237131
    Abstract: The present invention provides a method and apparatus for high yield improvements in programmable logic devices using redundancy. The present invention concerns a programmable logic device comprising a plurality of routings lines coupled to a plurality of logic blocks when programmed. During programming, a path is routed through the routing lines by programming the selected programmable elements. The selected programmable elements are located at each interconnect point between at least two routing lines or two segments of a routing lines along the path. The programmable elements include at least two interconnect circuits coupled in parallel. The programmable element is successfully programmed when at least one of the interconnect circuits is functional after programming.
    Type: Grant
    Filed: April 28, 1999
    Date of Patent: May 22, 2001
    Assignee: QuickLogic Corporation
    Inventors: James MacArthur, Timothy Lacey
  • Patent number: 6148390
    Abstract: A programmable logic device having redundant sets of logic blocks which are capable of being enabled or disabled. The programmable logic device includes a plurality of sets of logic blocks, a plurality of routing resources and a programming circuit. Good logic blocks are enabled and fully operational when programmed. Nonfunctional logic blocks are disabled, powered off and invisible to the programming software. Each set of logic blocks has a corresponding routing resource. The routing resource corresponding to an enabled set of logic blocks is capable of being configured to provide input and output data paths for the enabled set of logic blocks. The routing resource corresponding to a disabled set of logic blocks is capable of being configured to bypass the disabled set of the logic blocks. The programming circuit stores the configuration data for the routing resources and is capable of providing the configuration data to a routing resource that corresponds to an enabled set of logic blocks.
    Type: Grant
    Filed: June 12, 1996
    Date of Patent: November 14, 2000
    Assignee: QuickLogic Corporation
    Inventors: James MacArthur, Timothy M. Lacey
  • Patent number: 5925920
    Abstract: The present invention provides a method and apparatus for high yield improvements in programmable logic devices using redundancy. The present invention concerns a programmable logic device comprising a plurality of routings lines coupled to a plurality of logic blocks when programmed. During programming, a path is routed through the routing lines by programming the selected programmable elements. The selected programmable elements are located at each interconnect point between at least two routing lines or two segments of a routing lines along the path. The programmable elements include at least two interconnect circuits coupled in parallel. The programmable element is successfully programmed when at least one of the interconnect circuits is functional after programming.
    Type: Grant
    Filed: June 12, 1996
    Date of Patent: July 20, 1999
    Assignee: QuickLogic Corporation
    Inventors: James MacArthur, Timothy M. Lacey
  • Patent number: D732783
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: June 23, 2015
    Inventor: James MacArthur