Abstract: A pile guide for supporting a pile as it is driven into a substrate, comprises: a base frame; and a pile guide member (100) which is mounted on the base frame and defines a passageway with an inner peripheral surface (102) to which a plurality of elongate members (104) are attached. The plurality of elongate members (104) are configured to engage a pile and guide it in a predetermined direction through the passageway as it is driven into a substrate. At least one elongate member (104) and the inner peripheral surface (102) of the passageway have releasable inter-connecting profiles for releasably attaching the at least one elongate member (104) to the inner peripheral surface (102). The at least one elongate member (104) may readily be removed and replaced by a narrower/wider elongate member to accommodate piles of different diameter.

Abstract: Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.

Abstract: A system and method for distributing content to a display device is disclosed. In some embodiments, the display device comprises a processor that decodes visual content, a wireless interface that communicates with a wireless device associated with a viewer of the display device, and logic configured to receive information from the wireless device and purchase an item depicted on the display device for the viewer. In other embodiments, the method comprises receiving a request to broadcast content based, at least in part, on one or more variable metrics, monitoring a plurality of data sources that contain information related to the one or more variable metrics, and distributing the content to locations satisfying a relation utilizing the one or more variable metrics.

Abstract: Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.

Abstract: A method and apparatus are provided for dispatch group checkpointing in a microprocessor, including provisions for handling partially completed dispatch groups and instructions which modify system coherent state prior to completion. An instruction checkpoint retry mechanism is implemented to recover from soft errors in logic. The processor is able to dispatch fixed point unit (FXU), load/store unit (LSU), and floating point unit (FPU) or vector multimedia extension (VMX) instructions on the same cycle. Store data is written to a store queue when a store instruction finishes executing. The data is held in the store queue until the store instruction is checkpointed, at which point it can be released to the coherently shared level 2 (L2) cache.

Abstract: Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.

Abstract: A method and apparatus are provided for reducing the number of cycles required to checkpoint instructions in a multi-threaded microprocessor that has dispatch group checkpointing. A determination is made in a first stage of a checkpoint pipeline whether checkpointing can occur for a group of instructions. The results of processing the group of instructions flow to a second stage of the checkpoint pipeline regardless of whether the group of instructions is ready to checkpoint. If the group of instructions is ready to checkpoint, the group of instructions is checkpointed in a third stage of the checkpoint pipeline.

Abstract: A method and system for displaying visual content is disclosed. In some embodiments the system comprises a processor configured to process visual content that is to be displayed on the display, a storage coupled to the display and adapted to store the visual content, and a wireless interface configured to detect one or more viewers of the display when the one or more viewers are in physical proximity to the display.

Abstract: An article having a bearing surface with improved wear characteristics is provided. The article may be formed from a composition that includes a polymeric material, a lubricious and reinforcing additive, and a solid lubricant. Methods for forming the compositions and structures are also provided.

Abstract: An attachment for use in combination with a fishing pole. The attachment is attached to the fishing pole and is used to provide an automatic winding apparatus to retract a length of fishing line back around the reel after it has been cast out.

Abstract: An article having a bearing surface with improved wear characteristics is provided. The article may be formed from a composition that includes a polymeric material, a lubricious and reinforcing additive, and a solid lubricant. Methods for forming the compositions and structures are also provided.

Abstract: A shoe having retractable spikes including a shoe portion comprised of a sole portion having a heel portion and a toe portion. The heel portion and the toe portion each have a plurality of apertures therethrough in a spaced relationship. A pair of plates are disposed within the hollow interior of the sole portion. The pair of plates each have a plurality of spikes extending downwardly therefrom in a spaced relationship. The plurality of spikes are aligned with the plurality of apertures of the heel portion and the toe portion of the sole portion. The pair of plates each have a pair of springs extending downwardly therefrom which bias the plate upward. A deployment mechanism provides an extended orientation whereby the pair of plates extend downwardly against the biasing of the springs with the spikes extending through the apertures.