Abstract: A method of fabricating a single-crystal silicon photovoltaic cell includes providing a single-crystal silicon wafer and a structural support member. The single-crystal silicon wafer has a first major surface and a second major surface. Each major surface extends along a major surface plane. The single-crystal silicon wafer has a thickness greater than 100 micrometers and a dimension greater than 50 mm. The method further includes mounting the structural support member to the first major surface or to the second major surface. The method further includes reducing thickness of the single-crystal silicon wafer to a thickness less than or equal to 100 micrometers while the single-crystal silicon wafer is mounted to the structural support member. The method further includes providing the first major surface with a diffusion and a metalization grid and providing the second major surface with a back surface contact.

Abstract: A method of fabricating a single-crystal silicon photovoltaic cell includes providing a single-crystal silicon wafer and a structural support member. The single-crystal silicon wafer has a first major surface and a second major surface. Each major surface extends along a major surface plane. The single-crystal silicon wafer has a thickness greater than 100 micrometers and a dimension greater than 50 mm. The method further includes mounting the structural support member to the first major surface or to the second major surface. The method further includes reducing thickness of the single-crystal silicon wafer to a thickness less than or equal to 100 micrometers while the single-crystal silicon wafer is mounted to the structural support member. The method further includes providing the first major surface with a diffusion and a metalization grid and providing the second major surface with a back surface contact.

Abstract: A device for harvesting an external source of energy includes an electricity generating device and a flexure. The piezoelectric flexure has a first stable bowl-shaped position and a second stable bowl-shaped position. The electricity generating device generates electricity based on movement of the flexure. The flexure remains in the first stable bowl-shaped position until a force provided by the external source of energy causes the flexure to move from the first stable bowl-shaped position toward the second stable bowl-shaped position.

Abstract: A device for harvesting an external source of energy includes an electricity generating device, a flexure, and a first stop. Displacement of the flexure is limited by the first stop. The flexure has a vibration amplitude, wherein the vibration amplitude is amplitude the flexure would have if unconstrained by the first stop. The first stop allows the flexure to oscillate with a vibration amplitude that is higher than displacement of the flexure as limited by the first stop. The electricity generating device generates electrical energy while the first stop allows the flexure to oscillate with the higher vibration amplitude.

Abstract: A device for harvesting an external source of energy includes an electricity generating device, a flexure, and a restoring spring. The electricity generating device generates electricity based on movement of the flexure. The flexure has a first stable position. When disregarding presence of the restoring spring the flexure also has a second stable position different from the first stable position. The restoring spring is positioned so when the flexure snaps from the first stable position toward the second stable position the restoring spring provides a restoring spring force to restore the flexure toward the first stable position. Substantially greater force is needed to snap the flexure from the first stable position toward the second stable position to overcome the restoring spring force than is required to snap the flexure from the second stable position toward the first stable position.

Abstract: A module includes a flexible support member, a first piezoelectric element, a second piezoelectric element, an energy harvesting circuit, and a circuit element. The energy harvesting circuit includes a first rectifying device, a second rectifying device, a common output, and an energy storage device. The flexible support member includes an insulator having a pattern of wiring traces. The first piezoelectric element, the second piezoelectric element, the first rectifying device, and the second rectifying device are all mounted on and electrically connected to the flexible support member. The first rectifying device is electrically connected to the first piezoelectric element. The second rectifying device is electrically connected to the second piezoelectric element. The first rectifying device is electrically connected to the second rectifying device to provide the common output.

Abstract: In one embodiment a device comprises a composite structure that includes a piezoelectric flexure and a length-constraining element. The length-constraining element provides the piezoelectric flexure with a bowed shape. The piezoelectric flexure has a first stable bowed position and a second stable bowed position. The length-constraining element is one from the group consisting of a planar sheet and a columnar rod. In another embodiment a device comprises a piezoelectric flexure having a bowl shape. The piezoelectric flexure has a first stable bowl-shaped position and a second stable bowl-shaped position.

Abstract: A module includes a first piezoelectric element and first electronic device. The first piezoelectric provides physical support for said first electronic device. One embodiment includes a first insulating layer. The first insulating layer is mounted on the first piezoelectric element. The first electronic device is mounted on the first insulating layer for providing an electronic support function to the first piezoelectric element. In one embodiment the first electronic device includes a rectifier. One embodiment includes multiple contacts to the piezoelectric element each with its own rectifier. Another embodiment includes a stack of piezoelectric elements.

Abstract: An apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the product chips, at least one voltage regulator for each product chip. The voltage regulators provide a specified Vdd voltage to the product chips, whereby the Vdd voltage is substantially independent of current drawn by the product chips. The voltage regulators or other electronic means limit current to any product chip if it has a short. The voltage regulator circuit may be gated and variable and it may have sensor lines extending to the product chip. The test chips can also provide test functions such as test patterns and registers for storing test results.

Abstract: An apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the product chips, at least one voltage regulator for each product chip. The voltage regulators provide a specified Vdd voltage to the product chips, whereby the Vdd voltage is substantially independent of current drawn by the product chips. The voltage regulators or other electronic means limit current to any product chip if it has a short. The voltage regulator circuit may be gated and variable and it may have sensor lines extending to the product chip. The test chips can also provide test functions such as test patterns and registers for storing test results.

Abstract: An optical FET includes one or more light-responsive diodes stacked on the gate. Each diode includes a planar (horizontal) junction. The number of diodes is chosen to achieve a desired gate to source potential difference. An electrical connection connects the diode(s) to the source of the FET.

Abstract: Multichip semiconductor structures with consolidated circuitry are disclosed, along with programmable electrostatic discharge (ESD) protection circuits for chip input/output (I/O) nodes. The multichip structures include a first semiconductor chip having a first circuit at least partially providing a first predetermined circuit function, and a second semiconductor chip electrically and mechanically coupled to the first semiconductor chip. The second semiconductor device chip has a second circuit that at least partially provides a circuit function to the first circuit of the first semiconductor chip. In one embodiment, the first semiconductor chip includes a memory array chip, while the second semiconductor chip includes a logic chip wherein at least some peripheral circuitry necessary for accessing the memory array of the memory array chip resides within the logic chip. This allows the removal of redundant circuitry from identical chips of a multichip structure.

Abstract: An apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the product chips, at least one voltage regulator for each product chip. The voltage regulators provide a specified Vdd voltage to the product chips, whereby the Vdd voltage is substantially independent of current drawn by the product chips. The voltage regulators or other electronic means limit current to any product chip if it has a short. The voltage regulator circuit may be gated and variable and it may have sensor lines extending to the product chip. The test chips can also provide test functions such as test patterns and registers for storing test results.

Abstract: Integrated circuit chips are screened for susceptibility to latch-up by first applying power and ground to the chips to be tested while limiting current flow to a non-destructive compliance value. Next, the chips are irradiated with a pulse of radiation having an energy dose calibrated to trigger latch-up in latch-up sensitive chips. Upon termination of the radiation, the current is detected. Chips having current persisting at the compliance value are indicated as failing. The current in passing chips returns approximately to the original standby current value. In the preferred embodiment, the radiation is visible light and the radiation energy dose is selected to cause a percentage of chips to latch-up approximating the percentage of failures expected at burn-in.

Abstract: Multichip semiconductor structures with consolidated circuitry are disclosed, along with programmable electrostatic discharge (ESD) protection circuits for chip input/output (I/O) nodes. The multichip structures include a first semiconductor chip having a first circuit at least partially providing a first predetermined circuit function, and a second semiconductor chip electrically and mechanically coupled to the first semiconductor chip. The second semiconductor device chip has a second circuit that at least partially provides a circuit function to the first circuit of the first semiconductor chip. In one embodiment, the first semiconductor chip comprises a memory array chip, while the second semiconductor chip comprises a logic chip wherein at least some peripheral circuitry necessary for accessing the memory array of the memory array chip resides within the logic chip. This allows the removal of redundant circuitry from identical chips of a multichip structure.

Abstract: An optical FET includes one or more light-responsive diodes stacked on the gate. Each diode includes a planar (horizontal) junction. The number of diodes is chosen to achieve a desired gate to source potential difference. An electrical connection connects the diode(s) to the source of the FET.

Abstract: A fabrication method and resultant monolithic electronic module having a separately formed thin-film layer attached to a side surface. The fabrication method includes providing an electronic module composed of stacked integrated circuit chips. A thin-film layer is separately formed on a temporary support which is used to attach the thin-film layer to the electronic module. The disclosed techniques may also be used for attaching an interposer, which may include active circuity, to an electronic module. Specific details of the fabrication method, resulting multichip packages, and various thin-film structures are set forth.

Abstract: A fabrication method and resultant monolithic electronic module having a separately formed thin-film layer attached to a side surface. The fabrication method includes providing an electronic module composed of stacked integrated circuit chips. A thin-film layer is separately formed on a temporary support which is used to attach the thin-film layer to the electronic module. The disclosed techniques may also be used for attaching an interposer, which may include active circuity, to an electronic module. Specific details of the fabrication method, resulting multichip packages, and various thin-film structures are set forth.

Abstract: A multichip semiconductor structure and fabrication method having connect assemblies with fuses which facilitate burn-in stressing and electrical testing of the structure are presented. The structure comprises a multichip stack having standard transfer wire outs to an edge surface thereof. At least some wire outs to the edge surface have fuses electrically series connected thereto such that should an excessive current source/sink arise during burn-in stressing, the corresponding fuse will open circuit. A conductive structure is also disclosed that facilitates the formation of final, operational metallization wiring on the edge surface of the multichip structure prior to burn-in stressing and testing. This conductive structure includes a first conductive level and a second conductive level. The first conductive level has isolated conductors with ends disposed in close proximity.

Abstract: A multichip semiconductor structure and fabrication method having connect assemblies with fuses which facilitate burn-in stressing and electrical testing of the structure are presented. The structure comprises a multichip stack having standard transfer wire outs to an edge surface thereof. At least some wire outs to the edge surface have fuses electrically series connected thereto such that should an excessive current source/sink arise during burn-in stressing, the corresponding fuse will open circuit. A conductive structure is also disclosed that facilitates the formation of final, operational metallization wiring on the edge surface of the multichip structure prior to burn-in stressing and testing. This conductive structure includes a first conductive level and a second conductive level. The first conductive level has isolated conductors with ends disposed in close proximity.