Abstract: A device may receive network data identifying uplink/downlink packet loss percentage, uplink/downlink jitter, uplink/downlink latency, and uplink/downlink packet throughput associated with a slice of a network, and may set an uplink value for each of the uplink packet loss percentage, the uplink jitter, the uplink latency, and the uplink packet throughput. The device may multiply the uplink values by corresponding uplink weights to calculate an uplink cost, and may set a downlink value for each of the downlink packet loss percentage, the downlink jitter, the downlink latency, and the downlink packet throughput. The device may multiply the downlink values by corresponding downlink weights to calculate a downlink cost, and may calculate a total cost based on the uplink cost and the downlink cost. The device may cause another slice, with the same attributes as the slice, to be instantiated when the total cost satisfies a threshold for a time period.

Abstract: A device described herein, such as a User Plane Function (“UPF”) of a core network or some other network element, may receive traffic associated with a first User Equipment (“UE”) and a second UE. The traffic may include a first set of packets associated with the first UE and a second set of packets associated with the second UE. The first and second packets may be received in a first sequence. The device may generate a second sequence by re-sequencing the received traffic based on Quality of Service (“QoS”) parameters associated with the traffic, such as 5G QoS Identifier (“5QI”) values. The device may generate a third sequence by re-sequencing the second sequence based on parameters associated with at least the first UE or the second UE. The device may output at least a portion of the received traffic in accordance with the third sequence.

Abstract: A device may receive network data identifying uplink/downlink packet loss percentage, uplink/downlink jitter, uplink/downlink latency, and uplink/downlink packet throughput associated with a slice of a network, and may set an uplink value for each of the uplink packet loss percentage, the uplink jitter, the uplink latency, and the uplink packet throughput. The device may multiply the uplink values by corresponding uplink weights to calculate an uplink cost, and may set a downlink value for each of the downlink packet loss percentage, the downlink jitter, the downlink latency, and the downlink packet throughput. The device may multiply the downlink values by corresponding downlink weights to calculate a downlink cost, and may calculate a total cost based on the uplink cost and the downlink cost. The device may cause another slice, with the same attributes as the slice, to be instantiated when the total cost satisfies a threshold for a time period.

Abstract: A device described herein, such as a User Plane Function (“UPF”) of a core network or some other network element, may receive traffic associated with a first User Equipment (“UE”) and a second UE. The traffic may include a first set of packets associated with the first UE and a second set of packets associated with the second UE. The first and second packets may be received in a first sequence. The device may generate a second sequence by re-sequencing the received traffic based on Quality of Service (“QoS”) parameters associated with the traffic, such as 5G QoS Identifier (“5QI”) values. The device may generate a third sequence by re-sequencing the second sequence based on parameters associated with at least the first UE or the second UE. The device may output at least a portion of the received traffic in accordance with the third sequence.

Abstract: A device may receive network data identifying uplink/downlink packet loss percentage, uplink/downlink jitter, uplink/downlink latency, and uplink/downlink packet throughput associated with a slice of a network, and may set an uplink value for each of the uplink packet loss percentage, the uplink jitter, the uplink latency, and the uplink packet throughput. The device may multiply the uplink values by corresponding uplink weights to calculate an uplink cost, and may set a downlink value for each of the downlink packet loss percentage, the downlink jitter, the downlink latency, and the downlink packet throughput. The device may multiply the downlink values by corresponding downlink weights to calculate a downlink cost, and may calculate a total cost based on the uplink cost and the downlink cost. The device may cause another slice, with the same attributes as the slice, to be instantiated when the total cost satisfies a threshold for a time period.

Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

Abstract: A disclosed example to modulate slit stress in a semiconductor substrate includes a first controller to, after obtaining a wafer stress measurement of the semiconductor substrate, control a first process to apply a first material to the semiconductor substrate based on the wafer stress measurement, the semiconductor substrate including a slit between adjacent stacked transistor layers, the first material coating walls of the slit to reduce a first width of the slit between the adjacent stacked transistor layers to a second width; and a second controller to control a second process to apply a second material to the semiconductor substrate, the second material to be deposited in the second width of the slit, the first material and the second material to form a solid structure in the slit between the adjacent stacked transistor layers.

Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

Abstract: In one embodiment, an apparatus comprises a tier comprising alternating first and second layers, wherein the first layers comprise a first conductive material and the second layers comprise a first dielectric material; a lower metal layer below the tier; a bond pad above the tier, the bond pad coupled to the lower metal layer by a via extending through the tier; and a first channel formed through a portion of the tier, the first channel surrounding the via, the first channel comprising a second dielectric material.

Abstract: Convergence times associated with simulated annealing based (SA-based) optimization in wireless networks can be reduced by introducing an additional local or cell-level evaluation step into the evaluation of global solutions. In particular, new local solutions may be evaluated based on local performance criteria when the new solutions are in a global solution deemed to have satisfied a global performance criteria. New local solutions that satisfy their corresponding local performance criteria remain in the new global solution. New local solutions that do not satisfy their corresponding local performance criteria are replaced with a corresponding current local solution from a current global solution, thereby modifying the new global solution. The resulting modified global solution includes both new local solutions and current local solutions prior to being accepted as the current global solution for the next iteration.

Abstract: In one embodiment, an apparatus comprises a tier comprising alternating first and second layers, wherein the first layers comprise a first conductive material and the second layers comprise a first dielectric material; a lower metal layer below the tier; a bond pad above the tier, the bond pad coupled to the lower metal layer by a via extending through the tier; and a first channel formed through a portion of the tier, the first channel surrounding the via, the first channel comprising a second dielectric material.

Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

Abstract: A disclosed example to modulate slit stress in a semiconductor substrate includes a first controller to, after obtaining a wafer stress measurement of the semiconductor substrate, control a first process to apply a first material to the semiconductor substrate based on the wafer stress measurement, the semiconductor substrate including a slit between adjacent stacked transistor layers, the first material coating walls of the slit to reduce a first width of the slit between the adjacent stacked transistor layers to a second width; and a second controller to control a second process to apply a second material to the semiconductor substrate, the second material to be deposited in the second width of the slit, the first material and the second material to form a solid structure in the slit between the adjacent stacked transistor layers.

Abstract: A disclosed example to modulate slit stress in a semiconductor substrate includes controlling a first process to apply a first material to a semiconductor substrate. The semiconductor substrate includes a slit between adjacent stacked transistor layers. The first material coats walls of the slit to reduce a first width of the slit between the adjacent stacked transistor layers to a second width. A second process is controlled to apply a second material to the semiconductor substrate. The second material is to be deposited in the second width of the slit. The first material and the second material are to form a solid structure in the slit between the adjacent stacked transistor layers.

Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

Abstract: A disclosed example to modulate slit stress in a semiconductor substrate includes controlling a first process to apply a first material to a semiconductor substrate. The semiconductor substrate includes a slit between adjacent stacked transistor layers. The first material coats walls of the slit to reduce a first width of the slit between the adjacent stacked transistor layers to a second width. A second process is controlled to apply a second material to the semiconductor substrate. The second material is to be deposited in the second width of the slit. The first material and the second material are to form a solid structure in the slit between the adjacent stacked transistor layers.

Abstract: Methods and systems for predicting network performance include receiving a number of sets of data points of a number of network elements. Each of the number of sets of data points includes performance counter values and a performance indicator of a respective network element of the number of network elements. A global model representing a global relationship pattern between the performance indicator and the performance counter values is determined based on the number of sets of data points of the number of network elements. For each network element, residual features are determined based on error measures between the global model and the set of data points including the performance indicator and the performance counter values of the network element. The number of network elements are clustered into a number of clusters based on the determined residual features of the number of network elements.