Abstract: The functions of two virtual operating systems (e.g., S/370 VM and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. The S/370 processors are alien to the S/88 Operating System, i.e., not in its configuration tables. Means are provided to isolate partner pairs of S/88 processors from the S/88 Operating System and couple the S/88 processors directly to corresponding pairs of S/370 processors for interaction therewith, transparent to the S/88 Operating System.

Abstract: Instability effects over a wide range of static load current conditions in a conventional pulse width modulated (PWM) voltage regulator-converter/power converter circuit configuration having cascaded LC--LC filter networks are eliminated by replacing an inductor, in the averaging filter section of the voltage regulator-converter with the primary winding of a transinductor and by placing the secondary winding thereof in series with an inductor in the output filter section of the power converter. The aforementioned transinductor, in combination with other elements of the system, is designed and configurated such that the closed-loop stability characteristics approach that of a two pole system while maintaining the superior filtering characteristics of a four pole system.

Abstract: Disclosed herein is an improved pulse width modulated (PWM) voltage regulator-converter system which can function, alone, as a switched voltage regulator system or in combination with a switched power converter, synchronized therewith to form an improved voltage regulator-converter/power converter system. In the pulse width modulated voltage regulator-converter embodiment of the invention, secondary windings of a "current mode" regulator-converter interstage transformer are coupled to regulator-converter power transistors in a push-push circuit configuration. Signals generated by a system clock means and an error signal, derived from the output of an averaging filter, drive a pulse width modulated control means connected to the primary windings of the regulator-converter interstage transformer to thereby increase the maximum regulated output voltage of the voltage regulator-converter system after conditioning in the averaging filter.