Abstract: A new connector implemented with connector pins to reduce crosstalk significantly improves memory channel electrical performance for next generation DDR (double data rate) technology. To reduce crosstalk the connector pins include pins with three different pin shapes, including two differently shaped signal pins and a ground pin that combines the shapes of the signal pins. The shaped pins enables them to be positioned in a connector so that each signal pin can have its own independent and separate signal return path on a single ground pin. In this manner, crosstalk can be significantly reduced.

Abstract: Disclosed herein are integrated circuit (IC) supports with microstrips, and related embodiments. For example, an IC support may include a plurality of microstrips and a plurality of conductive segments. Individual ones of the conductive segments may be at least partially over at least two microstrips, a dielectric material may be between the plurality of microstrips and the plurality of conductive segments, and the conductive segments are included in a tape.

Abstract: A memory subsystem triggers dynamic switching for memory devices to provide access to active memory devices and prevent access to inactive memory devices. Dynamic switching enables a single bus to switch between multiple memory devices whose capacity otherwise exceeds the capacity of the single bus. A switch can be mounted in a memory module or directly on a motherboard alongside the memory devices. A memory controller can toggle a chip select signal as a single control signal to drive the switch. Each switch includes pairs of field effect transistors (FETs), including any of CMOS, NMOS and PMOS FETs. The switch electrically isolates inactive memory devices to prevent access without the need to electrically short the devices.

Abstract: Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.

Abstract: Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.

Abstract: Decision feedback equalization (DFE) training time in a memory device is reduced through the use of a hybrid search to select values of tap coefficients for taps in the DFE. The hybrid search includes two searches. A first search is performed to identify initial values of tap coefficients, a second search uses the initial values of tap coefficients to find the final values of tap coefficients.

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to facilitating increased clock speeds on a substrate by lowering the impedance of traces that provide clock signals to components such as DRAM. For example, embodiments may include a substrate with a first layer and a second layer parallel to the first layer with a first trace coupled with the first layer in a routing configuration and a second trace coupled with the second layer in the routing configuration, where the routing configuration of the first trace and the second trace substantially overlap each other with respect to an axis perpendicular to the first layer and the second layer, and where the first trace and the second trace are electrically coupled by a first and a second electrical coupling perpendicular to the first layer and the second layer.

Abstract: Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.

Abstract: According to examples, a memory module with module rows of conductive contacts can enable multiple memory channels to be connected to the same memory module. In one example, a memory module includes a printed circuit board (PCB) having a first face, a second face, and an edge to be received by a connector. The memory module includes a plurality of memory chips on at least one of the first and second faces of the PCB. The memory module includes two or more rows of conductive contacts on each of the first and second faces of the PCB, the two rows including a first row of conductive contacts proximate to the edge of the PCB to be received by the connector, and a second row of conductive contacts between the first row and a second edge of the PCB opposite to the first edge.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate, that comprises a bumpout region on a first surface of the package substrate, and a pin region on a second surface of the package substrate. In an embodiment, a data path from the bumpout region to the pin region is included in the electronic package. In an embodiment, a ground path brackets the data path from the bumpout region to the pin region.

Abstract: Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.

Abstract: Examples described herein relate to a system that includes: a circuit board comprising a plurality of layers, first and second conductive connections, first and second trace portions, first, second, and third routings, and a via wherein: the first conductive connection is coupled to the first trace portion, the second conductive connection is coupled to the second trace portion, the first routing is formed in a first layer of the plurality of layers, the second routing is formed in a second layer of the plurality of layers, the third routing is formed in the first layer of the plurality of layers, a portion of the first routing overlaps with a portion of the second routing to provide a capacitive region, and the via conductively couples a portion of the second routing overlaps with a portion of the third routing.

Abstract: A system has an unmatched communication architecture for a unidirectional command bus and compensates for drift on the command bus based on data provided on a bidirectional data bus. The memory device has an oscillator to measure drift or an amount of delay for the command bus over a time interval. The memory device can return a value over the data bus to the memory controller based on the delay measured with the oscillator. Based on receiving the value, the memory controller can adjust configuration settings for communication on the command bus.

Abstract: Examples described herein relate to a system that includes: a circuit board comprising a plurality of layers and at least one conductive connection. In some examples, the at least one conductive connection is connected to a layer of the plurality of layers. In some examples, at least one layer of the plurality of layers comprises a conductive material. In some examples, the at least two layers of the plurality of layers comprise conductive material that extend in an axis towards the at least one conductive connection but do not overlap with the at least one layer of the plurality of layers comprising the conductive material.

Abstract: Examples described herein relate to a system that includes: a first signal pin and a first ground pin adjacent to the first signal pin. In some examples, the first signal pin comprises a first portion, a second portion, and a third portion. In some examples, the first ground pin comprises a first portion, a second portion, and a third portion, the second portion of the first signal pin comprises a vertical mount, the second portion of the first ground pin comprises a vertical mount, and the second portion of the first signal pin and the second portion of the first ground pin are arranged proximate one another.

Abstract: A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.

Abstract: An integrated circuit package includes a substrate with traces for high speed communication that are subject to crosstalk. The traces include overlapping pads on different layers of the substrate, which can increase the mutual capacitance of the signal lines, which will offset the mutual inductance. Thus, the overlapping pads can reduce the crosstalk between the signal traces.

Abstract: Examples described herein relate to a system that includes: a first device comprising a motherboard; a second device comprising a dual in-line memory module (DIMM); and an arrangement of a signal pin and ground pin pair coupled to the motherboard and DIMM wherein portions of the signal pin and ground pin pair are proximate each other.

Abstract: Systems, apparatuses and methods may provide for a memory module that includes a dynamic random access memory (DRAM), a first plurality of contact pads positioned along a first side of the DRAM, a first plurality of L-shaped contacts, wherein each of the first plurality of L-shaped contacts is soldered to one of the first plurality of contact pads, a second plurality of contact pads positioned along a second side of the DRAM, and a second plurality of L-shaped contacts, wherein each of the second plurality of L-shaped contacts is soldered to one of the second plurality of contact pads.

Abstract: Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.