Abstract: An I/O node for a computer system including an integrated graphics engine and integrated I/O hub. An input/output node that is implemented on an integrated circuit chip includes a transceiver unit, a graphics engine and an I/O hub. The transceiver unit may receive and transmit packets on a point-to-point link of a packet interface. The graphics engine may be coupled to receive graphics packets received by the transceiver unit and may render digital image information in response to receiving the graphics packets. The I/O hub may be coupled to receive I/O packets corresponding to packets received by the transceiver unit and may initiate bus cycles corresponding to the I/O packets upon a peripheral bus. The packet interface link may be a point-to-point HyperTransport™ link including a first and second set of uni-directional wires which may convey control and data packets over the same wires.

Abstract: An I/O node for a computer system including an integrated graphics engine. An input/output node is implemented upon an integrated circuit chip. The I/O node includes a first transceiver unit, a second transceiver unit, a packet tunnel, a graphics engine and a graphics interface. The first transceiver unit may receive and transmit packet transactions on a first link of a packet bus and the second transceiver unit may receive and transmit packet transactions on a second link. The packet tunnel may convey selected packet transactions between the first and the second transceiver unit. The graphics engine may receive graphics packet transactions from the first transceiver unit and may render digital image information in response to receiving the graphics transactions. The graphics interface may receive additional graphics packet transactions from the first transceiver unit and may translate the additional graphics packet transactions into transactions suitable for transmission upon a graphics bus.

Abstract: A communication system which includes more efficient bus utilization for higher data throughput. The communication system includes various logic devices connected to a system bus. The communication system intelligently utilizes unused system bus bandwidth for improved performance. The communication system includes a receive buffer, a memory, a central processing unit (CPU), a direct memory access (DMA) controller, and a bus arbiter each preferably coupled to the system bus. The buffer is operable to generate a low priority DMA transfer request when any amount of data is stored in the buffer. The buffer is also operable to generate a high priority DMA transfer request when a certain threshold or amount of data is stored in the buffer, i.e., when a certain "water-level" has been reached. When the buffer generates the low priority DMA request, the DMA controller and/or bus determine if the system bus is otherwise not being utilized, e.g.