Abstract: Various exemplary embodiments relate to a method performed by a pulsewidth modulation (PWM) controller, the method including: receiving a control input including PWM parameters; producing inputs to a digital serializer, wherein the inputs result in a digital serializer output that is pulsewidth modulated according to the PWM parameters; receiving a feedback control input; and modifying inputs to a digital serializer based upon the feedback control input.

Abstract: Various exemplary embodiments relate to a method performed by a pulsewidth modulation (PWM) controller, the method including: receiving a control input including PWM parameters; producing inputs to a digital serializer, wherein the inputs result in a digital serializer output that is pulsewidth modulated according to the PWM parameters; receiving a feedback control input; and modifying inputs to a digital serializer based upon the feedback control input.

Abstract: An increased connector port density assembly is disclosed for providing more connector ports than would normally fit on a faceplate. The increased connector port density assembly includes a stationary board and an extendable board connected to the stationary board on rails and with cabling. The extendable board has a first and second set of forward facing connector assemblies. The first set accessible when the extendable board is in either the retracted or extended position, whereas the second set of connector assemblies is accessible when the extendable board is in the extended position. The increased connector port density assembly is particularly useful for overcoming faceplate connector area availability limitations known in the art.

Abstract: An increased connector port density assembly is disclosed for providing more connector ports than would normally fit on a faceplate. The increased connector port density assembly includes a stationary board and an extendable board connected to the stationary board on rails and with cabling. The extendable board has a first and second set of forward facing connector assemblies. The first set accessible when the extendable board is in either the retracted or extended position, whereas the second set of connector assemblies is accessible when the extendable board is in the extended position. The increased connector port density assembly is particularly useful for overcoming faceplate connector area availability limitations known in the art.

Abstract: A system and method for dynamic frequency adjustment for interoperability of differential clock recovery, including one or more of the following: a frequency generator for receiving a frequency reference clock signal and generating a plurality of frequency signals by operating on the frequency reference clock signal, the plurality of frequencies signals being output from the frequency generator and each having a different frequency; a flexible distributor for receiving the plurality of frequency signals from the frequency generator and selecting ones of said plurality of frequency signals and transmitting said selected ones of said plurality of frequency signals; and a plurality of differential units, each for receiving one of said selected ones of said plurality of frequency signals, each for applying a differential signal to said selected ones of said plurality of frequency signals, and each for adding time stamps to the selected ones of said plurality of frequency signals and outputting respective time sta

Abstract: A system and method for dynamic frequency adjustment for interoperability of differential clock recovery, including one or more of the following: a frequency generator for receiving a frequency reference clock signal and generating a plurality of frequency signals by operating on the frequency reference clock signal, the plurality of frequencies signals being output from the frequency generator and each having a different frequency; a flexible distributor for receiving the plurality of frequency signals from the frequency generator and selecting ones of said plurality of frequency signals and transmitting said selected ones of said plurality of frequency signals; and a plurality of differential units, each for receiving one of said selected ones of said plurality of frequency signals, each for applying a differential signal to said selected ones of said plurality of frequency signals, and each for adding time stamps to the selected ones of said plurality of frequency signals and outputting respective time sta

Abstract: A system and method for dynamic frequency adjustment for interoperability of differential clock recovery, comprising: a frequency generator for receiving a frequency reference clock signal and generating a plurality of frequency signals, the plurality of frequency signals being output from the frequency generator and each having a different frequency; a flexible distributor for receiving the plurality of frequency signals from the frequency generator, and transmitting selected frequency signals; and a plurality of differential units, each for receiving the selected frequency signals, applying a differential signal to the selected frequency signals, adding time stamps to the selected frequency signals, and outputting respective time stamped differential selected frequency signals.

Abstract: A clock distribution mechanism for circuit emulation applications, and related method, including one or more of the following: a plurality of digitally controlled oscillators, each of the plurality of digitally controlled oscillators receiving one or more Ethernet packets and generating a recovered clock from the one or more Ethernet packets; a multiplexer for receiving the recovered clocks generated by the plurality of digitally controlled oscillators, selecting a one of the recovered clocks generated by the plurality of digitally controlled oscillators, and outputting the selected one of the recovered clocks; a normalizer that receives a frequency of the selected one of the recovered clocks and generates a normalized frequency output based on the received frequency of the selected one of the recovered clocks and outputs the normalized frequency output; a clock source selector for receiving a plurality of input clock sources, one of the input clock sources being the normalized frequency output of the normali

Abstract: A method for incorporating a queuing device as a lossless processing stage in a network device in a communications network, comprising: monitoring a depth of a queue in the queuing device, the queue for receiving packets from an upstream device within the network device, the queuing device acting as a discard point by discarding packets when the queue is full; and, if the depth passes a predetermined threshold, sending a message to the upstream device to reduce a rate at which packets are sent to the queuing device to prevent the queue from filling and thereby preventing packet discarding and loss by the queuing device.

Abstract: A system and method for dynamic frequency adjustment for interoperability of differential clock recovery, including one or more of the following: a frequency generator for receiving a frequency reference clock signal and generating a plurality of frequency signals by operating on the frequency reference clock signal, the plurality of frequencies signals being output from the frequency generator and each having a different frequency; a flexible distributor for receiving the plurality of frequency signals from the frequency generator and selecting ones of said plurality of frequency signals and transmitting said selected ones of said plurality of frequency signals; and a plurality of differential units, each for receiving one of said selected ones of said plurality of frequency signals, each for applying a differential signal to said selected ones of said plurality of frequency signals, and each for adding time stamps to the selected ones of said plurality of frequency signals and outputting respective time sta

Abstract: A clock distribution mechanism for circuit emulation applications, and related method, including one or more of the following: a plurality of digitally controlled oscillators, each of the plurality of digitally controlled oscillators receiving one or more Ethernet packets and generating a recovered clock from the one or more Ethernet packets; a multiplexer for receiving the recovered clocks generated by the plurality of digitally controlled oscillators, selecting a one of the recovered clocks generated by the plurality of digitally controlled oscillators, and outputting the selected one of the recovered clocks; a normalizer that receives a frequency of the selected one of the recovered clocks and generates a normalized frequency output based on the received frequency of the selected one of the recovered clocks and outputs the normalized frequency output; a clock source selector for receiving a plurality of input clock sources, one of the input clock sources being the normalized frequency output of the normali

Abstract: A method for resetting a component of an off-card assembly in a redundant system, the redundant system having first and second control plane cards coupled to the off-card assembly by respective serial interfaces, each serial interface including a respective status line and a respective clock line, each status line for providing a respective activity indication and a respective reset instruction, each clock line for providing a respective clock signal, the method comprising: monitoring respective activity indications and clock signals from the first and second control plane cards by the off-card assembly to determine which of the first and second control plane cards is an active card; and, selecting the reset instruction from the active card to reset the component, thereby resolving any conflict between respective reset instructions.

Abstract: A method and apparatus are provided for storing the boot configuration PROM of a microprocessor in an FPGA. The boot interface of the microprocessor, such as an I2C interface, leads to the FPGA instead of to a PROM. The boot configuration is stored as an image in the FPGA, and the microprocessor accesses the boot configuration using its normal boot interface. In this way, a dedicated boot PROM is not needed, saving real estate on the card on which the microprocessor is located. The boot configuration is also more easily modified, such as for version upgrades or diagnostics, than if the boot configuration were stored on a dedicated PROM. Different boot configurations may be stored as software images on a separate housekeeper processor, for loading into the FPGA.

Abstract: The method described herein is a more efficient way to transmit non-user data over a SPI 4.2 interface. During single PHY mode, the transmission occurs between single ports, eliminating the need for a port address in the control word portion of the SPI 4.2 data word. Consequently, the address bits can be used to indicate the type of data being transmitted in single PHY mode, either user or non-user data. Since non-user data is transmitted periodically, the bandwidth granularity is improved by using bandwidth when required for the non-user data as opposed to dedicating bandwidth to it. The bandwidth granularity is reduced to remain within the specifications for any type of SPI 4.2 packet, including OC-192.

Abstract: A method and apparatus of communicating data packets across the midplane of an electronic system in which the packets are partitioned into segments of a predetermined size and then serialized to a predetermined width. The serialized packets are transmitted, in phase staggered segments, across the midplane on a respective channel, received into receiving end and the serialized segments that have traversed the midplane, are deserialized and reassembled into the original data packet.