Abstract: A bicycle includes a chainstay protector having an upper surface including a valley, a first peak, and a second peak. The first peak extends upwardly from the valley toward the chain and has a first contact surface positioned to contact the chain a first height above the valley. The second peak extends upwardly from the valley toward the chain and has a second contact surface positioned to contact the chain a second height above the valley. The first contact surface is spaced from the second contact surface by a gap that is at least 5 times the first height. Each of the first and second contact surfaces has a length that is less than the length of the gap and less than two times a pitch of the chain.

Abstract: A bicycle includes a chainstay protector having an upper surface including a valley, a first peak, and a second peak. The first peak extends upwardly from the valley toward the chain and has a first contact surface positioned to contact the chain a first height above the valley. The second peak extends upwardly from the valley toward the chain and has a second contact surface positioned to contact the chain a second height above the valley. The first contact surface is spaced from the second contact surface by a gap that is at least 5 times the first height. Each of the first and second contact surfaces has a length that is less than the length of the gap and less than two times a pitch of the chain.

Abstract: A bicycle includes a chainstay protector having an upper surface including a valley, a first peak, and a second peak. The first peak extends upwardly from the valley toward the chain and has a first contact surface positioned to contact the chain a first height above the valley. The second peak extends upwardly from the valley toward the chain and has a second contact surface positioned to contact the chain a second height above the valley. The first contact surface is spaced from the second contact surface by a gap that is at least 5 times the first height. Each of the first and second contact surfaces has a length that is less than the length of the gap and less than two times a pitch of the chain.

Abstract: A bicycle includes a chainstay protector having an upper surface including a valley, a first peak, and a second peak. The first peak extends upwardly from the valley toward the chain and has a first contact surface positioned to contact the chain a first height above the valley. The second peak extends upwardly from the valley toward the chain and has a second contact surface positioned to contact the chain a second height above the valley. The first contact surface is spaced from the second contact surface by a gap that is at least 5 times the first height. Each of the first and second contact surfaces has a length that is less than the length of the gap and less than two times a pitch of the chain.

Abstract: A bicycle includes a chainstay protector having an upper surface including a valley, a first peak, and a second peak. The first peak extends upwardly from the valley toward the chain and has a first contact surface positioned to contact the chain a first height above the valley. The second peak extends upwardly from the valley toward the chain and has a second contact surface positioned to contact the chain a second height above the valley. The first contact surface is spaced from the second contact surface by a gap that is at least 5 times the first height. Each of the first and second contact surfaces has a length that is less than the length of the gap and less than two times a pitch of the chain.

Abstract: A method that optimizes system performance using performance monitors is presented. The method gathers thread performance data using performance monitors for threads running on either a first ISA processor or a second ISA processor. Multiple first processors and multiple second processors may be included in a single computer system. The first processors and second processors can each access data stored in a common shared memory. The gathered thread performance data is analyzed to determine whether the corresponding thread needs additional CPU time in order to optimize system performance. If additional CPU time is needed, the amount of CPU time that the thread receives is altered (increased) so that the thread receives the additional time when it is scheduled by the scheduler. In one embodiment, the increased CPU time is accomplished by altering a priority value that corresponds to the thread.

Abstract: Code handling, such as interpreting language instructions or performing “just-in-time” compilation, is performed using a heterogeneous processing environment that shares a common memory. In a heterogeneous processing environment that includes a plurality of processors, one of the processors is programmed to perform a dedicated code-handling task, such as perform just-in-time compilation or interpretation of interpreted language instructions, such as Java. The other processors request code handling processing that is performed by the dedicated processor. Speed is achieved using a shared memory map so that the dedicated processor can quickly retrieve data provided by one of the other processors.

Abstract: A computer implemented method and system for optimizing thermal performance of a computer system. An identification of a set of processor cores associated with the computer system is made and a thermal index is requested for each of the set of processor cores to form a set of thermal indexes. Proximity information and conductive property information associated with the set of processors is loaded and software is mapped to execute on an optimal processor core form the set of processor cores based the set of thermal indexes, proximity information, and conductive property information.

Abstract: A computer system's multiple processors are managed as devices. The operating system accesses the multiple processors using processor device modules loaded into the operating system to facilitate a communication between an application requesting access to a processor and the processor. A device-like access is determined for accessing each one of the processors similar to device-like access for other devices in the system such as disk drives, printers, etc. An application seeking access to a processor issues device-oriented instructions for processing data, and in addition, the application provides the processor with the data to be processed. The processor processes the data according to the instructions provided by the application.

Abstract: A computer implemented method, data processing system, and computer usable code are provided for generation of hardware thermal profiles for a set of processors. Sampling is performed of the thermal states of the set of processors during the execution of a set of workloads to create sampled information. The sampled information and thermal characteristics of the set of processors are combined and a thermal index is generated based on the sampled information and characteristics of the set of processors.

Abstract: A computer implemented method, data processing system, computer usable code, and apparatus are provided for generation of software thermal profiles for applications executing on a set of processors. Sampling is performed of the hardware operations occurring in a set of processors during the execution of a set of workloads to create sampled information. A thermal index is then generated based on the sampled information.

Abstract: A computer implemented method, data processing system, computer usable code, and apparatus are provided for optimizing the thermal performance of a computer system. A set of processor cores associated with the computer system are identified. A thermal index is requested for each of the set of processor cores and the processor cores are ranked based on the thermal index. Software is then mapped to execute on an optimal processor core form the set of processor cores based on the ranking.

Abstract: A computer implemented method, data processing system, and computer usable code are provided for optimizing thermal performance of a computer system. Identification of a set of system resources associated with the computer system is performed and a thermal index is requested for each of the set of system resources to form a set of thermal indexes. An action from a set of actions is identified to reduce resource utilization. The action is implemented to reduce a thermal state of the computer system.

Abstract: Code handling, such as interpreting language instructions or performing “just-in-time” compilation, uses a heterogeneous processing environment that shares a common memory. In a heterogeneous processing environment that includes a plurality of processors, one of the processors is programmed to perform a dedicated code-handling task, such as perform just-in-time compilation or interpretation of interpreted language instructions, such as Java. The other processors request code handling processing that is performed by the dedicated processor. Speed is achieved using a shared memory map so that the dedicated processor can quickly retrieve data provided by one of the other processors.