Abstract: An apparatus (10) for generating a sequence of blocks of randomly permuted multi-bit data elements includes an input register (12) that produces a repeating block of distinct input data elements from which output blocks of permuted data elements are generated. A permutation logic unit (14) forms an output data element from each input data element in accordance with random data stored in random code memories (16). The output data element produced by the permutation logic unit is supplied to an output register (18). The manner in which the random data is selected and applied by the permutation logic unit ensures that each of the data elements in the input block will be mapped into an output position in the output block.

Abstract: High precision transmitted navigational data as encrypted data transmitted by global positioning (GPS) satellites is made unavailable in regions designated as hostile and during desired intervals, while allowing the data to be available outside the hostile region. All satellites in the GPS constellation transmit the high precision navigational data in encrypted form. However, only the satellites that are not visible to the hostile region transmit the periodic key necessary to decrypt the data. The periodic key changes after a predetermined time interval. During a given time interval the same key value is used by all satellites for encryption of the high precision navigational data. A receiver can obtain the current periodic key from any visible satellite which is transmitting the periodic key. This key is then used to decrypt the high precision navigational data from that satellite and all other visible satellites.

Abstract: There is disclosed encryption apparatus for generating a deterministic psuedorandom keystream of data derived from a secret key and a prearranged initial state and modulo-N adding the random data to plain text data to form a cipher text data stream to be transmitted. In order to reduce spoofing, which is the ability to alter received plain text by altering the transmitted cipher text there is means responsive to the plain text for altering a portion of the plain text data relative to corresponding cipher text data according to a permutation function which varies according to a selected keystream whereby one who does not possess said secret key cannot decrypt said cipher text and while preventing spoofing.

Abstract: Each of first N flip-flop stages, where N is an integer greater than one, has steered thereto an appropriate one of N bits of the data to be transmitted by a transmit write counter and a first N stage decoder under control of a transmit write clock. A transmit read counter under control of a transmit read clock steers the stored bits to a transmit data bus by means of a first multiplexer and first logic circuitry under control of a transmit read counter and a transmit channel timing signal. Each of second N flip-flop stages has steered thereto an appropriate one of N bits of received data by a receive write counter and a second N stage decoder under control of a receive write clock. A receive read counter under control of a receive read clock steers the stored bits to a receive data bus by means of a second multiplexer and second logic circuitry under control of the receive read counter.

Abstract: The phasing circuit transfers digital data from an external interface circuit to an internal interface circuit with no bit errors and no violation of bit count integrity under control of an external clock having a given frequency and a given phase and an internal clock having a frequency equal to the given frequency and a phase that is different than the given phase.

Abstract: Two D-type flip flops have a clock and a 1/4-bit delayed clock coupled to the D inputs of respective ones of the two flip flops to provide a +/- phase error of a present sample of digital data coupled to the clock inputs of the two flip flops and a second signal indicating a large/small phase error of the present sample of the data. A third signal indicating a +/- phase error of a previous state of the data is provided and a fourth signal indicating a large/small error of the previous state of the data is provided. A read only memory is responsive to the first, second, third and fourth signals in accordance with a given set of rules to produce a phase error signal with a clockwise change of phase states of the data providing a negative frequency error signal and a counter-clockwise change of phase states of the data providing a positive frequency error signal.

Abstract: A first generator provides a reference pulse train having a predetermined reference frequency. A second generator including a voltage controlled oscillator provides a bit clock having a repetition frequency locked to the repetition frequency of the bits of digital data. A first divider coupled to the first generator divides the reference frequency by a selected one of a first division factor and a second division factor different than the first division factor. A fourth divider coupled to the second generator divides the repetition frequency of the bit clock by a selected one of a third division factor and a fourth division factor different than the first, second and third division factors. A phase comparator coupled to the first and second dividers compare the phase of the output signals of the first and second dividers and produces a control signal proportional to the phase difference between the output signals of the first and second dividers.

Abstract: The demodulator produces an inphase digital reference signal having the form cos A by means of an analog-to-digital converter and a quadrature digital reference signal having the form sin A by means of an N-stage shift register coupled to the converter. An inphase digital FSK signal having the form cos B is provided by a second analog-to-digital converter and a quadrature digital FSK signal having the form sin B is produced by a second N-stage shift register. A first read only memory responsive to the inphase and quadrature digital reference signals and the inphase and quadrature FSK signals produce an inphase code signal and a quadrature code signal for estimating the value of (B - A). A first M-stage shift register delays the inphase code signal and a second M-stage shift register delays the quadrature code signal.

Abstract: An asynchronous digital time division multiplexer and demultiplexer combination at one communication terminal is disclosed that will multiplex first N asynchronous source data signals having a first mixture of different bit rates into a transmitted synchronous data stream having a predetermined fixed data format and a given bit rate greater than the total of the bit rates of the source data and to demultiplex second N asynchronous source data signals having a second mixture of different bit rates from a received synchronous data stream having the predetermined fixed data format and the given bit rate.

Abstract: An automatic channel assignment circuit in a controlling association with an asynchronous or synchronous digital time division multiplexer and demultiplexer combination at one communication terminal to assign channels of transmitted and received synchronous data streams to asynchronous or synchronous source data signals in a manner to minimize temporary data memory regardless of the number of different bit rates of the source data signals by assigning the data signals to channels of the associated one of the transmitted and received data streams so that the bits of each of the data signals tend to have equal spacing throughout the bits of the associated one of the transmitted and received data streams. Each of the transmitted and received data streams have a predetermined fixed data format with respect to the channels and a given bit rate greater than the total of the bit rates of the source signals.

Abstract: A transmit phase locked loop receives data to be transmitted having a bit rate equal to a first given one of a predetermined number of different bit rates. A diphase demodulator responds to the transmit phase locked loop and the data to be transmitted to provide output data for transmission. A receive write timing signal and a receive read timing signal is coupled to a receive phase locked loop to compare the phase relation of the two timing signals. A diphase modulator responds to received data having a bit rate equal to a second given one of the predetermined number of different bit rates and a clock signal provided by the receive phase locked loop to provide output data for utilization. The first given one of different bit rates and the second given one of different bit rates may have equal or different bit rates.