Abstract: A method of estimating power consumption of an electronic device is performed by a processing device. The estimating includes estimating a power consumption of a gate-level implementation of an electronic device design. The estimating further includes independently calculating for each of a plurality of implementation-invariant nodes of the design an incremental power dissipation associated with that node.

Abstract: A method of designing an integrated circuit includes receiving a placement database of logic devices of an electronic device design that includes first and second logic devices. The method further includes determining a first timing window associated with a first state transition of the first logic device, and a second timing window associated with a second state transition of the second logic device. In the event that the first and second timing windows overlap, the placement database is modified, thereby reducing interaction of the first and second logic devices.

Abstract: A method of estimating power consumption of an electronic device is performed by a processing device. The estimating includes estimating a power consumption of a gate-level implementation of an electronic device design. The estimating further includes independently calculating for each of a plurality of implementation-invariant nodes of the design an incremental power dissipation associated with that node.

Abstract: The present invention is directed to methods for optimizing package and silicon co-design of an integrated circuit. A composite bump pattern for an integrated circuit is created based on a first library including at least one bump pattern template. PCB and Die constraints of the integrated circuit are then reviewed. A partial package design for the integrated circuit is generated based on a second library including at least one partial package template. A partial silicon design for said integrated circuit is started. A full package design for the integrated circuit is then completed. A full silicon design for the integrated circuit is completed.

Abstract: A method for re-using diffused cell-based IP blocks in a structured application specific integrated circuit comprising the steps of (A) implementing one or more blocks of intellectual property (IP) using a plurality of cell-based building blocks and (B) providing one or more alternative views for at least one of the one or more blocks of intellectual property.