Patents by Inventor James Moscola

James Moscola has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8826058
    Abstract: A Delay-tolerant Asynchronous Interface (DANI) is typically used to make the clock domains for reusable silicon intellectual property (IP) cores completely independent of each other. In fact, a DANI-wrapped IP core usually appears to its environment as if it were clockless. This property is necessary to address the variability in data transmission-time between source and destination. This variability is a result of increased lack of predictability in today's leading-edge manufacturing processes. A DANI wrapper can be applied to the IP core that is the source of data to be transmitted or it can be applied to the IP core that is the destination of that data. The transmission time over the route between source and destination may vary more than a single clock period.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: September 2, 2014
    Assignee: Blendics, Inc.
    Inventors: Jerome R. Cox, Jr., George Engel, James Moscola, Thomas J. Chaney
  • Patent number: 7093023
    Abstract: A reprogrammable packet processing system for processing a stream of data is disclosed herein. A reprogrammable data processor is implemented with a programmable logic device (PLD), such as a field programmable gate array (FPGA), that is programmed to determine whether a stream of data applied thereto includes a string that matches a redefinable data pattern. If a matching string is found, the data processor performs a specified action in response thereto. The data processor is reprogrammable to search packets for the presence of different data patterns and/or perform different actions when a matching string is detected. A reconfiguration device receives input from a user specifying the data pattern and action, processes the input to generate the configuration information necessary to reprogram the PLD, and transmits the configuration information to the packet processor for reprogramming thereof.
    Type: Grant
    Filed: May 21, 2002
    Date of Patent: August 15, 2006
    Assignee: Washington University
    Inventors: John Lockwood, Ronald Loui, James Moscola, Michael L Pachos
  • Publication number: 20030221013
    Abstract: A reprogrammable packet processing system for processing a stream of data is disclosed herein. A reprogrammable data processor is implemented with a programmable logic device (PLD), such as a field programmable gate array (FPGA), that is programmed to determine whether a stream of data applied thereto includes a string that matches a redefinable data pattern. If a matching string is found, the data processor performs a specified action in response thereto. The data processor is reprogrammable to search packets for the presence of different data patterns and/or perform different actions when a matching string is detected.
    Type: Application
    Filed: May 21, 2002
    Publication date: November 27, 2003
    Inventors: John Lockwood, Ronald Loui, James Moscola, Michael Pachos