Patents by Inventor James MOSSMAN

James MOSSMAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dynamic configuration of processor sub-components
    Patent number: 12222797
    Abstract: The disclosed method includes observing a utilization of a target sub-component of a functional unit of a processor using a control circuit coupled to the target sub-component. The method also includes detecting that the utilization is outside a desired utilization range and throttling one or more sub-components of the functional unit to reduce a power consumption of the functional unit. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: February 11, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: James Mossman, Robert Cohen, Sudherssen Kalaiselvan, Tzu-Wei Lin
  • DYNAMIC CONFIGURATION OF PROCESSOR SUB-COMPONENTS
    Publication number: 20240201777
    Abstract: The disclosed method includes observing a utilization of a target sub-component of a functional unit of a processor using a control circuit coupled to the target sub-component. The method also includes detecting that the utilization is outside a desired utilization range and throttling one or more sub-components of the functional unit to reduce a power consumption of the functional unit. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: December 19, 2022
    Publication date: June 20, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: James Mossman, Robert Cohen, Sudherssen Kalaiselvan, Tzu-Wei Lin
  • Processor with multiple op cache pipelines
    Patent number: 11907126
    Abstract: A processor employs a plurality of op cache pipelines to concurrently provide previously decoded operations to a dispatch stage of an instruction pipeline. In response to receiving a first branch prediction at a processor, the processor selects a first op cache pipeline of the plurality of op cache pipelines of the processor based on the first branch prediction, and provides a first set of operations associated with the first branch prediction to the dispatch queue via the selected first op cache pipeline.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: February 20, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Robert B. Cohen, Tzu-Wei Lin, Anthony J. Bybell, Sudherssen Kalaiselvan, James Mossman
  • PROCESSOR WITH MULTIPLE OP CACHE PIPELINES
    Publication number: 20220100663
    Abstract: A processor employs a plurality of op cache pipelines to concurrently provide previously decoded operations to a dispatch stage of an instruction pipeline. In response to receiving a first branch prediction at a processor, the processor selects a first op cache pipeline of the plurality of op cache pipelines of the processor based on the first branch prediction, and provides a first set of operations associated with the first branch prediction to the dispatch queue via the selected first op cache pipeline.
    Type: Application
    Filed: December 9, 2020
    Publication date: March 31, 2022
    Inventors: Robert B. COHEN, Tzu-Wei LIN, Anthony J. BYBELL, Sudherssen KALAISELVAN, James MOSSMAN