Patents by Inventor James MUNGER

James MUNGER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Chip scale package
    Patent number: 11887924
    Abstract: The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: January 30, 2024
    Assignee: Cirrus Logic Inc.
    Inventors: Craig McAdam, Jonathan Taylor, Douglas Macfarlane, John Kerr, James Munger, John Pavelka, Steven A. Atherton
  • POWER CONVERTER CIRCUITRY
    Publication number: 20230344351
    Abstract: The present disclosure relates to power converter circuitry, and in particular to power converter circuitry for providing a supply voltage to a load such as amplifier circuitry. In one aspect the invention provides a system comprising: amplifier circuitry; and power converter circuitry for receiving a supply voltage and providing an output voltage to the amplifier circuitry, the power converter circuitry comprising: a control loop for regulating an output voltage of the power converter circuitry in accordance with a target output voltage value; and controller circuitry configured to adjust the target output voltage value if the supply voltage to the power converter circuitry is within a first predefined threshold of a requested output voltage of the power converter circuitry.
    Type: Application
    Filed: April 13, 2023
    Publication date: October 26, 2023
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Alastair M. BOOMER, John B. BOWLERWELL, James MUNGER, Andrew J. HOWLETT
  • CHIP SCALE PACKAGE
    Publication number: 20230088252
    Abstract: The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.
    Type: Application
    Filed: November 23, 2022
    Publication date: March 23, 2023
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Craig MCADAM, Jonathan TAYLOR, Douglas MACFARLANE, John KERR, James MUNGER, John PAVELKA, Steven A. ATHERTON
  • Chip scale package
    Patent number: 11562952
    Abstract: The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: January 24, 2023
    Assignee: Cirrus Logic, Inc.
    Inventors: Craig McAdam, Jonathan Taylor, Douglas Macfarlane, John Kerr, James Munger, John Pavelka, Steven A. Atherton
  • CHIP SCALE PACKAGE
    Publication number: 20220246514
    Abstract: The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.
    Type: Application
    Filed: April 30, 2021
    Publication date: August 4, 2022
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Craig MCADAM, Jonathan TAYLOR, Douglas MACFARLANE, John KERR, James MUNGER, John PAVELKA, Steven A. ATHERTON