Patents by Inventor James Murguia

James Murguia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Conflict free radiation tolerant storage cell
    Patent number: 6573773
    Abstract: A Single Event Upset (SEU) resistant latch circuit that uses the Single Event Resistant Topology (SERT) comprises a first circuit module electrically coupled to a second circuit module. In the SERT-1 embodiment, the first circuit module has two output terminals, including four cross-coupled p-channel (PMOS) transistors coupled with two n-channel (NMOS) transistors. The second circuit module has two output terminals, including four cross-coupled p-channel (PMOS) transistors coupled with two n-channel (NMOS) transistors. These four output terminals satisfy a set of state equations that can be used to obtain the SERT-1 State Table. In the SERT-2 embodiment, the first circuit module has two output terminals, including four cross-coupled n-channel (NMOS) transistors coupled with two p-channel (PMOS) transistors. The second circuit module has two output terminals, including four cross-coupled n-channel (NMOS) transistors coupled with two p-channel (PMOS) transistors.
    Type: Grant
    Filed: February 2, 2001
    Date of Patent: June 3, 2003
    Assignee: University of New Mexico
    Inventors: Gary Maki, Kenneth Haas, Shi Quan, James Murguia
  • Conflict free radiation tolerant storage cell
    Publication number: 20010033189
    Abstract: A Single Event Upset (SEU) resistant latch circuit that uses the Single Event Resistant Topology (SERT) comprises a first circuit module electrically coupled to a second circuit module. In the SERT-1 embodiment, the first circuit module has two output terminals, including four cross-coupled p-channel (PMOS) transistors coupled with two n-channel (NMOS) transistors. The second circuit module has two output terminals, including four cross-coupled p-channel (PMOS) transistors coupled with two n-channel (NMOS) transistors. These four output terminals satisfy a set of state equations that can be used to obtain the SERT-1 State Table. In the SERT-2 embodiment, the first circuit module has two output terminals, including four cross-coupled n-channel (NMOS) transistors coupled with two p-channel (PMOS) transistors. The second circuit module has two output terminals, including four cross-coupled n-channel (NMOS) transistors coupled with two p-channel (PMOS) transistors.
    Type: Application
    Filed: February 2, 2001
    Publication date: October 25, 2001
    Inventors: Gary Maki, Kenneth Hass, Shi Quan, James Murguia