Abstract: A memory cell responsive to a write enable signal for storing write signals present on a pair of write bit lines and responsive to a read enable signal for presenting stored data on a pair of read sense lines further includes a timed, active write load. The memory cell includes first and second NPN bipolar transistors having commonly connected emitters, and cross-coupled bases and collectors; and first and second PNP bipolar transistors configured as loads for the pair of NPN bipolar transistors. Write transistors are provided responsive to the write enable signal for draining current from a selected one of the first or second nodes. Transistors connected as diodes between the PNP bases and each of the cross-coupled NPN nodes are responsive to the current draining effected by the write transistors for biasing both of the first and second PNP transistors into an active mode of operation.