Abstract: A system and method for efficiently handling instruction execution ordering. In various embodiments, a processor includes multiple execution lanes, each executing instructions of a particular type, which are not executed by one or more of the other execution lanes. The instruction queue includes one queue for each particular execution lane. Control logic identifies a current youngest age used in allocated entries of the multiple queues, and determines a starting age based on the identified current youngest age and the number of instructions to be issued. Beginning with the determined starting age, ages (in program order) are assigned to a group of instructions being allocated in the multiple queues. Ages of entries in the multiple queues are updated for instructions not being issued based on the number of instructions being issued. Instructions being issued have age differences between them below a threshold.

Abstract: A system and method for efficiently handling maintenance requests among multiple processors. In various embodiments, a given processor of multiple processors receives a maintenance request. If maintenance requests are not currently being blocked, then the given processor determines a type of the maintenance request and updates one or more maintenance type counters based on the type. If one or more counters exceed a threshold, an indication is generated specifying maintenance requests received at a later time are to be held. The received maintenance request is processed. Different types of maintenance requests are used for invalidating entries in the instruction cache, for invalidating entries in a TLB and for synchronizing page table updates. Afterward, software applications continue processing. Forward progress of the software applications is measured using one or more metrics. If forward progress has been achieved, then one or more maintenance type counters are reset.

Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, and another core may be implemented at a lower maximum performance, but may be optimized for efficiency. Additionally, in some embodiments, some features of the instruction set architecture implemented by the processor may be implemented in only one of the cores that make up the processor. If such a feature is invoked by a code sequence while a different core is active, the processor may swap cores to the core the implements the feature. Alternatively, an exception may be taken and an exception handler may be executed to identify the feature and activate the corresponding core.

Abstract: In some embodiments, a system includes a register file, a plurality of clock gating circuits, a free list circuit, and a register allocation adjustment circuit. The register file includes a plurality of registers. The clock gating circuits control receipt of a clock signal at respective regions of registers. The free list circuit performs multiple search operations in parallel to identify unallocated registers. The register allocation adjustment circuit implements a mapping between registers identified by the free list circuit and registers of the register file such that the multiple search operations identify whether registers of a first region are unallocated prior to identifying whether registers of a second region are unallocated. As a result, a region of the register file is less likely to be in use during a particular clock cycle and a clock gating circuit may prevent a clock signal from being received at the region.

Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, and another core may be implemented at a lower maximum performance, but may be optimized for efficiency. Additionally, in some embodiments, some features of the instruction set architecture implemented by the processor may be implemented in only one of the cores that make up the processor. If such a feature is invoked by a code sequence while a different core is active, the processor may swap cores to the core the implements the feature. Alternatively, an exception may be taken and an exception handler may be executed to identify the feature and activate the corresponding core.

Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, and another core may be implemented at a lower maximum performance, but may be optimized for efficiency. Additionally, in some embodiments, some features of the instruction set architecture implemented by the processor may be implemented in only one of the cores that make up the processor. If such a feature is invoked by a code sequence while a different core is active, the processor may swap cores to the core the implements the feature. Alternatively, an exception may be taken and an exception handler may be executed to identify the feature and activate the corresponding core.

Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. The processor may support multiple processor states (PStates). Each PState may specify an operating point (e.g. a combination of supply voltage magnitude and clock frequency), and each PState may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core. The context switch may be performed using a special purpose register (SPR) interconnect. Each processor core in a given processor may be coupled to the SPR interconnect to permit access to the external SPRs.

Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. The processor may support multiple processor states (PStates). Each PState may specify an operating point (e.g. a combination of supply voltage magnitude and clock frequency), and each PState may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core. The context switch may be performed using a special purpose register (SPR) interconnect. Each processor core in a given processor may be coupled to the SPR interconnect to permit access to the external SPRs.

Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, and another core may be implemented at a lower maximum performance, but may be optimized for efficiency. Additionally, in some embodiments, some features of the instruction set architecture implemented by the processor may be implemented in only one of the cores that make up the processor. If such a feature is invoked by a code sequence while a different core is active, the processor may swap cores to the core the implements the feature. Alternatively, an exception may be taken and an exception handler may be executed to identify the feature and activate the corresponding core.

Abstract: A cache memory that completes an in-flight operation with another cache that collides with a snoop operation, rather than canceling the in-flight operation. Operations to the cache comprise a query pass and one or more finish passes. When the cache detects a snoop query intervening between the query pass and a finish pass of the in-flight operation, the cache generates a more up-to-date status for the snoop query that takes into account the tag status to which the in-flight finish pass will update the implicated cache line. This is necessary because otherwise the snoop query might not see the affect of the in-flight finish pass status update. This allows the in-flight finish pass to complete instead of being cancelled and the snoop finish pass to correctly update the status after the in-flight finish pass, and to provide modified data from the cache line to the externally snooped transaction.

Abstract: A cache memory that notifies other functional blocks in the microprocessor that a miss has occurred potentially N clocks sooner than the conventional method, where N is the number of stages in the cache pipeline. The multiple pass cache receives a plurality of busy indicators from resources needed to complete various transaction types. The cache distinguishes between a first set of resources needed to complete a transaction when its cache line address hits in the cache and a second set of resources needed to complete the transaction type when the address misses in the cache. If none of the second set of resources for the type of the transaction type is busy on a miss, then the cache immediately signals a miss rather than retrying the transaction by sending it back through the cache pipeline and causing N additional clock cycles to occur before signaling the miss.

Abstract: A preferred embodiment of the present invention includes a memory caching system that uses a method for allocating blocks of memory by: determining if the contents at a selected memory address are stored in the cache by comparing the selected memory address to the addresses stored in the directory, if the selected memory address is not in the cache, allocating a place in the directory for selected address, wherein, if a place in the directory for an address having the same cache line as the selected memory address is in the process of allocating or has been previously allocated, the selected memory address is allocated to that location of the pending or previous allocation.

Abstract: A computer processor (110) automatically generates block-size operand references during execution of standard instructions. As such a standard instruction is executed, the processor (110) continually examines the number of bytes to be moved (342) and the relative alignment of the operand address (352). At any time during instruction execution, if the operand address is zero modulo the block size, and at least a block sized number of bytes remain to be moved (354), the operand transfer is marked as a block-sized reference.This provides a convenient method for generating block-sized memory references to/from the targeted address space, independent of cache modes such as copyback, write-through, or non-cacheable. This may produce burst accesses, maximizing performance of the data transfer. Additionally, cache memory writes can be optimized to avoid cache line fill reads.

Abstract: A cache locking mechanism is implemented so that portions of the cache may be locked to protect critical instructions or data residing within the cache. Such a cache may be associated with a processor chip, coupled to a data processing system. The cache locking mechanism forces de-allocation of cache entries to the unlocked section of the cache. However, allocation of cache entries is performed regardless of whether or not an entry resides within the locked portion, provided that there exists invalid entries within the locked portion.

Abstract: After a portion of a cache line has been zone written from a processor core (102) to a cache array (105), a read access received from the processor core (102) for one or more bytes within the cache line corresponding to the zone written data can be satisfied before a cache fill operation initiated by the zone written operation is completed. If the read access is for one or more bytes of the cache line which was not previously zone written, then the requested data is passed directly from the filling bus (113) to the processor core (102) as soon as it becomes valid on the filling bus (113). If the read access is for one or more bytes of the zone written data, then those one or more bytes are read from the cache array (105) to the processor core (102) regardless of the progress of the cache fill. All read accesses to filling cache lines are serviced in the minimum amount of time by satisfying the access immediately upon availability of only the exact portion requested.