Patents by Inventor James N. Kruchowski

James N. Kruchowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8855499
    Abstract: In an n-node optical communications system, energy harvesting photodetectors at each node receive extraneous electromagnetic wavelengths that are not used for communication or other purposes by the associated node. The energy harvesting photodetectors convert the unused electromagnetic energy into reusable electrical energy. The harvested electrical energy may be used as auxiliary power at the node or elsewhere in the communication system, or stored in a battery, capacitor, or other energy storage device. The system may be used in an “all-to-all” broadcast and select communication scheme or in some other broadcast and select interconnect system that has extraneous wavelengths at node receivers.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: October 7, 2014
    Assignee: Mayo Foundation for Medical Education and Research
    Inventors: Vladimir Sokolov, James N. Kruchowski, Mark A. Nelson, Nathan E. Harff
  • Patent number: 8540434
    Abstract: A connector assembly for optically coupling a first optical device mounted on a first substrate to a second optical device mounted on a second substrate, where the first and second substrates are orthogonally oriented to each other, is presented. The connector assembly includes two connectors. The first connector has an optical waveguide array. The optical waveguide array further includes multiple parallel optical waveguides that are continuously redirected by a mirror oriented at a 45 degree angle to the optical waveguides. Likewise, the second connector also has an optical waveguide array further include multiple parallel optical waveguides continuously redirected by a mirror oriented at a 45 degree angle to the optical waveguides. The first connector is oriented orthogonally to the second connector and the first and second connectors are optically welded together in a back-to-back configuration.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: September 24, 2013
    Assignee: MAYO Foundation for Medical Education and Research
    Inventors: James N. Kruchowski, Vladimir Sokolov, Mark A. Nelson
  • Publication number: 20130202292
    Abstract: In an n-node optical communications system, energy harvesting photodetectors at each node receive extraneous electromagnetic wavelengths that are not used for communication or other purposes by the associated node. The energy harvesting photodetectors convert the unused electromagnetic energy into reusable electrical energy. The harvested electrical energy may be used as auxiliary power at the node or elsewhere in the communication system, or stored in a battery, capacitor, or other energy storage device. The system may be used in an “all-to-all” broadcast and select communication scheme or in some other broadcast and select interconnect system that has extraneous wavelengths at node receivers.
    Type: Application
    Filed: January 21, 2011
    Publication date: August 8, 2013
    Applicant: Mayo Foundation for Medical Education and Research
    Inventors: Vladimir Sokolov, James N. Kruchowski, Mark A. Nelson, Nathan E. Harff
  • Publication number: 20110274394
    Abstract: A connector assembly for optically coupling a first optical device mounted on a first substrate to a second optical device mounted on a second substrate, where the first and second substrates are orthogonally oriented to each other, is presented. The connector assembly includes two connectors. The first connector has an optical waveguide array. The optical waveguide array further includes multiple parallel optical waveguides that are continuously redirected by a mirror oriented at a 45 degree angle to the optical waveguides. Likewise, the second connector also has an optical waveguide array further include multiple parallel optical waveguides continuously redirected by a mirror oriented at a 45 degree angle to the optical waveguides. The first connector is oriented orthogonally to the second connector and the first and second connectors are optically welded together in a back-to-back configuration.
    Type: Application
    Filed: January 15, 2010
    Publication date: November 10, 2011
    Inventors: James N. Kruchowski, Vladimir Sokolov, Mark A. Nelson
  • Patent number: 5258576
    Abstract: A generic chip carrier is described which includes, as integral parts, a voltage bus and a plurality of terminating resistors connected between the voltage bus and signal traces on the carrier. The voltage bus wraps around the chip carrier, thus providing a large area of metal. Through the selective use of the terminating resistors, the generic carrier can be customized for a particular type of integrated circuit, i.e., source or destination termination of signals. A signal trace may be customized by "opening" the terminating resistor with a current spike applied by a standard electrical probe. Spare bonding pads and terminating resistors are placed at intervals about the periphery of the carrier as insurance against defective or mistakenly removed terminating resistors.
    Type: Grant
    Filed: January 3, 1992
    Date of Patent: November 2, 1993
    Assignee: Cray Research, Inc.
    Inventors: Eugene F. Neumann, Melvin C. August, James N. Kruchowski, Stephen Nelson, Richard R. Steitz
  • Patent number: 5185502
    Abstract: The present invention provides an improved method for manufacturing circuit boards with high power, high density interconnects. Printed circuit board technology, integrated circuit technology, and heavy-build electroless plating are combined to produce multilayer circuit boards comprised of substrates with different interconnect densities. In the higher density substrates, thick metallized layers are built-up by combining additive and subtractive techniques. These thicker foils minimize DC voltage drop so that conductors can run for longer distances. The conductors are substantially more square than their thin film equivalents, thus providing better performance for high frequency signals. Power distribution capabilities are enhanced by the present invention, so that circuit boards fully populated with dense, high-speed, high-power integrated circuits can easily be supplied with their necessary power requirements.
    Type: Grant
    Filed: October 16, 1990
    Date of Patent: February 9, 1993
    Assignee: Cray Research, Inc.
    Inventors: Lloyd T. Shepherd, Melvin C. August, James N. Kruchowski
  • Patent number: 5162743
    Abstract: Apparatus and method for determining the electrical length of a signal flow path, such as a twisted-pair conductor, to create conductors of the same electrical length are disclosed. The term electrical length refers to a certain physical distance for a length of conductor for which an electrical signal travels, or propagates along the conductor, in a specified amount of time. The apparatus preferably includes a Time Domain Reflectometer 25 (including pulse generator means 30 and electrical response display means 20) which is cooperatively connected to a first end of a conductor pair 51 under test. The conductor pair 51 is inserted through a ground plane 60 or other impedance changing device. Means to mark or cut 62 the conductor 51 are located within the ground plane 60 or as close as possible to the point at which the impedance is changed. Processing means 40 are utilized to adjust the conductor 51 length relative to the ground plane 60.
    Type: Grant
    Filed: November 9, 1990
    Date of Patent: November 10, 1992
    Assignee: Cray Research, Inc.
    Inventors: James N. Kruchowski, Melvin C. August, John B. Eder
  • Patent number: 5127986
    Abstract: The present invention provides an improved method for manufacturing circuit boards with high power, high density interconnects. Printed circuit board technology, integrated circuit technology, and heavy-build electroless plating are combined to produce multilayer circuit boards comprised of substrates with different interconnect densities. In the higher density substrates, thick metallized layers are built-up by combining additive and subtractive technique. These thicker foils minimize DC voltage drop so that conductors can run for longer distances. The conductors are substantially more square than their thin film equivalents, thus providing better performance for high frequency signals. Power distribution capabilities are enhanced by the present invention, so that circuit boards fully populated with dense, high-speed, high-power integrated circuits can easily be supplied with their necessary power requirements.
    Type: Grant
    Filed: December 1, 1989
    Date of Patent: July 7, 1992
    Assignee: Cray Research, Inc.
    Inventors: Melvin C. August, Lloyd T. Shepherd, James N. Kruchowski
  • Patent number: 5122620
    Abstract: A generic chip carrier is described which includes, as integral parts, a voltage bus and a plurality of terminating resistors connected between the voltage bus and signal traces on the carrier. The voltage bus wraps around the chip carrier, thus providing a large area of metal. Through the selective use of the terminating resistors, the generic carrier can be customized for a particular type of integrated circuit, i.e., source or destination termination of signals. A signal trace may be customized by "operating" the terminating resistor with a current spike applied by a standard electrical probe. Spare bonding pads and terminating resistors are placed at intervals about the periphery of the carrier as insurance against defective or mistakenly removed terminating resistors.
    Type: Grant
    Filed: June 25, 1991
    Date of Patent: June 16, 1992
    Assignee: Cray Research Inc.
    Inventors: Eugene F. Neumann, Melvin C. August, James N. Kruchowski, Stephen Nelson, Richard R. Steitz
  • Patent number: 4949453
    Abstract: A generic chip carrier is described which includes, as integral parts, a voltage bus and a plurality of terminating resistors connected between the voltage bus and signal traces on the carrier. The voltage bus wraps around the chip carrier, thus providing a large area of metal. Through the selective use of the terminating resistors, the generic carrier can be customized for a particular type of integrated circuit, i.e., source or destination termination of signals. A signal trace may be customized by "opening" the terminating resistor with a current spike applied by a standard electrical probe. Spare bonding pads and terminating resistors are placed at intervals about the periphery of the carrier as insurance against defective or mistakenly removed terminating resistors.
    Type: Grant
    Filed: June 15, 1989
    Date of Patent: August 21, 1990
    Assignee: Cray Research, Inc.
    Inventors: Eugene F. Neumann, Melvin C. August, James N. Kruchowski, Stephen Nelson, Richard R. Steitz
  • Patent number: 4786392
    Abstract: A fixture is provided which cleans a plasma etcher of a type that has a holding member with a surface which holds wafers that are to be etched, and an enclosing member which encloses the holding member to form a chamber for the plasma. This fixture operates to produce a large voltage change near the enclosing member and thereby enable the cleaning of the enclosing member by the plasma itself. To achieve such a large voltage change, the fixture is configured to fit inside of the enclosing member, provide a surface which is substantially larger than the surface of the holding member, and make electrical contact with the surface of the holding member. Preferably, the surface provided by the fixture is at least 50% larger than the surface of the holding member.
    Type: Grant
    Filed: April 23, 1987
    Date of Patent: November 22, 1988
    Assignee: Unisys Corporation
    Inventors: James N. Kruchowski, Robert K. Sakurai
  • Patent number: RE34395
    Abstract: A generic chip carrier is described which includes, as integral parts, a voltage bus and a plurality of terminating resistors connected between the voltage bus and signal traces on the carrier. The voltage bus wraps around the chip carrier, thus providing a large area of metal. Through the selective use of the terminating resistors, the generic carrier can be customized for a particular type of integrated circuit, i.e., source or destination termination of signals. A signal trace may be customized by "opening" the terminating resistor with a current spike applied by a standard electrical probe. Spare bonding pads and terminating resistors are placed at intervals about the periphery of the carrier as insurance against defective or mistakenly removed terminating resistors.
    Type: Grant
    Filed: December 11, 1991
    Date of Patent: October 5, 1993
    Assignee: Cray Research, Inc.
    Inventors: Eugene F. Neumann, Melvin C. August, James N. Kruchowski, Stephen Nelson, Richard R. Steitz