Abstract: A memory efficient method for translating and displaying sub-picture images for DVD data. The method uses less memory than prior systems. Rather than storing the sub-picture image in a memory, the method decodes and displays the sub-picture images on-the-fly. Subsequent sub-picture pixels are being translated as a given sub-picture pixel is being displayed on a display.

Abstract: A memory efficient method for translating and displaying sub-picture images for DVD data. The method uses less memory than prior systems. Rather than storing the sub-picture image in a memory, the method decodes and displays the sub-picture images on-the-fly. Subsequent sub-picture pixels are being translated as a given sub-picture pixel is being displayed on a display.

Abstract: A memory efficient method for translating and displaying sub-picture images for DVD data. The method uses less memory than prior systems. Rather than storing the sub-picture image in a memory, the method decodes and displays the sub-picture images on-the-fly. Subsequent sub-picture pixels are being translated as a given sub-picture pixel is being displayed on a display.

Abstract: An interface circuit that facilitates communication between a DSP and decoder in a disc system or other application. The interface circuit is programmable so multiple communication interfaces can be supported without requiring additional specialized logic uniquely tailored for each particular communication interface. Sector and countdown-type data transfers are supported by the interface circuit.

Abstract: A variable length decoder comprises a bitstream feeder connected to a header analyzer, and a block data decoder coupled to the feeder. The bitstream feeder includes a barrel shifter to output a 32-bit bitstream to the header analyzer, block data decoder and control circuit. The header analyzer detects the start codes of the MPEG header layers and decodes the parameters of the MPEG layers contained in the encoded bitstream. Further, the header analyzer decodes the quantization factors of 8.times.8 pixel data which have been converted into 64 DCT coefficients. The block data decoder includes a macroblock decoder connected to a block decoder. The macroblock decoder outputs a header.sub.-- start signal, and activates the block decoder. The block decoder includes a code table for decoding 64 coefficients in each of the 6 block layers based on a binary pattern of a predetermined number of bits of the bitstream. The six block layers are decoded within 384 clock cycles.

Abstract: A high bit rate start code monitoring, searching and detecting circuit includes a Least Significant Bit (LSB) zero counter, a Most Significant Bit (MSB) zero counter, first and second adders, first and second registers, a comparator, a start code detector, and a start code decoder. The LSB zero counter counts the number of consecutive zero bits from the least significant bit while the MSB zero counter counts the number of consecutive zero bits starting with the most significant bit. A LSB zero count output is added with a prescribed value by the first adder to arrive at a Zero.sub.-- Bits.sub.-- Shifted.sub.-- Out (ZBSO) value, which is saved in the first register. A MSB zero count output is added with the stored value of the ZBSO value during the subsequent clock cycle. If the summed (S) value is greater than or equal to 23, then the start code detector is enabled. The start code detector can detect parts of a start code contained in two separate bitstreams or a start code embedded in a bitstream.