Patents by Inventor James N. Snead

James N. Snead has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8448029
    Abstract: A multiprocessor system with multiple watchdog timers, the timers causing all the processors in the system to concurrently process a common interrupt signal asserted by any of the watchdog timers timing out. The processors, in response to the common interrupt signal, store data residing in their local memories into a memory common to all the processors. The stored data is then stored in a permanent storage device for later analysis. Thereafter, all of the processors are reset.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: May 21, 2013
    Assignee: LSI Corporation
    Inventor: James N. Snead
  • Publication number: 20100287320
    Abstract: Described embodiments provide interprocessor communication between at least two processors of an integrated circuit, each processor running at least one task. For each processor, a proxy task is generated corresponding to each task running on each other processor. A task identifier for each task, and a look-up table having each task identifier associated with each other processor running the task is also generated. When a message is sent from a source task to a destination task that is running on a different processor than the source task, the source task communicates with the proxy task of the destination task. The proxy task appends the task identifier for the destination task to the message and sends the message to an interprocessor communication interface. Based on the task identifier, the processor running the destination task is determined and the destination task retrieves the message.
    Type: Application
    Filed: May 6, 2009
    Publication date: November 11, 2010
    Inventors: Carlos Querol, James N. Snead, Michael S. Hicken, Randal S. Rysavy, Carl E. Forhan
  • Publication number: 20100235558
    Abstract: A multiprocessor system with multiple watchdog timers, the timers causing all the processors in the system to concurrently process a common interrupt signal asserted by any of the watchdog timers timing out. The processors, in response to the common interrupt signal, store data residing in their local memories into a memory common to all the processors. The stored data is then stored in a permanent storage device for later analysis. Thereafter, all of the processors are reset.
    Type: Application
    Filed: March 11, 2009
    Publication date: September 16, 2010
    Inventor: James N. Snead
  • Patent number: 7293196
    Abstract: A method, apparatus, and system for preserving the cache data of redundant storage controllers, by copying the recorded data blocks and the associated cache tags in the primary cache memory of a storage controller to a secondary cache memory of an alternate, redundant storage controller, wherein upon a failure occurring in the primary cache memory of any of the storage controllers, subsequent storage requests from a host, previously intended for processing by the failed storage controller, are processed through the secondary cache memory of a non-failed, redundant storage controller that contains the failed storage's controller cache data and cache tags.
    Type: Grant
    Filed: May 7, 2003
    Date of Patent: November 6, 2007
    Assignee: Xiotech Corporation
    Inventors: Michael S. Hicken, James N. Snead
  • Patent number: 7162587
    Abstract: A method, and apparatus for recovering cache data of a failed redundant storage controller and reestablishing redundancy by mirroring cache data of a primary cache memory of a first storage controller in a secondary cache memory of another storage controller. Upon a failure occurring in a storage controller, the failure is detected and, in response, a structured list of cache tags is created in the controller where having the secondary cache that is the mirror of the primary cache of the failed controller.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: January 9, 2007
    Inventors: Michael S. Hiken, Steven M. Howe, James N. Snead
  • Publication number: 20040153727
    Abstract: A method, and apparatus for recovering cache data of a failed redundant storage controller and reestablishing redundancy by mirroring cache data of a primary cache memory of a first storage controller in a secondary cache memory of another storage controller. Upon a failure occurring in a storage controller, the failure is detected and, in response, a structured list of cache tags is created in the controller where having the secondary cache that is the mirror of the primary cache of the failed controller.
    Type: Application
    Filed: May 5, 2003
    Publication date: August 5, 2004
    Inventors: Michael S. Hicken, Steven M. Howe, James N. Snead
  • Publication number: 20030212864
    Abstract: A method, apparatus, and system for preserving the cache data of redundant storage controllers, by copying the recorded data blocks and the associated cache tags in the primary cache memory of a storage controller to a secondary cache memory of an alternate, redundant storage controller, wherein upon a failure occurring in the primary cache memory of any of the storage controllers, subsequent storage requests from a host, previously intended for processing by the failed storage controller, are processed through the secondary cache memory of a non-failed, redundant storage controller that contains the failed storage's controller cache data and cache tags.
    Type: Application
    Filed: May 7, 2003
    Publication date: November 13, 2003
    Inventors: Michael S. Hicken, James N. Snead
  • Publication number: 20030212865
    Abstract: A method and apparatus for flushing a write cache includes receiving a read or a write storage request, determining whether the storage request comprises a full or partial hit with data stored in a write cache one or more lines, some of which may be dirty. If the hit is partial and the one or more lines of the data are dirty, flushing the dirty data. If the hit is full or partial and any of the write cache lines are not dirty, and the storage request is a write request, flushing the dirty write cache lines, invalidating the non dirty write cache line, writing the storage request data into the write cache as a new write cache line and marking the new write cache line dirty. If the hit is full, all write cache lines are marked dirty, and the storage request is a write request, overlaying the cache write line with the storage request data and marking the write cache line as dirty.
    Type: Application
    Filed: May 8, 2003
    Publication date: November 13, 2003
    Inventors: Michael S. Hicken, James N. Snead