Abstract: Example embodiments use hydrophilic substances to absorb moisture from the air passing through the vent cover. The vent cover is recommended to be used along with a fan to regulate the air flow through the vent cover. The vent cover has holes, and the holes are filled with the hydrophilic material (i.e., hydrogel or polyacrylamide beads). Once enough moisture from the air passes through the vent cover, the vent cover seals itself and prevents air from flowing. The hydrophilic material allows the water to evaporate over time and thus effectively removes the seal.

Abstract: An arbitration circuit and method for a multiport high speed memory in a computer microprocessor. A plurality of addresses are provided to a plurality of ports. The addresses are decoded in a plurality of decoders. The decoded output lines are compared in a comparison circuitry to determine if one or more of the ports is requesting access to the same memory line, and a comparison bit indicative of a match is outputted. If asserted, the comparison bit disables a line driver so that only one of the wordlines in a particular memory line is driven at any one time.

Abstract: A cache controller tag random access memory (RAM) is configured into two ways, each way including tag and valid-bit storage for associatively searching a directory for cache data-array addresses. The two ways, a right way and a left way, each store tag addresses. There are two lines selected during a line fill to one of the ways. A least recently used (LRU) pointer selects which way to fill on a line fill cycle. The right way is selected for a line fill in response to right hit signal provided that the LRU pointer points to the right way. The LRU pointer is flipped to point to the left way upon the filling of the right line of the right way. The left way is selected for a line fill in response to a left hit signal provided that the LRU pointer points to the left way. The LRU pointer is flipped to point to the right way upon the filling of the left line of the left way.

Abstract: A cache controller tag random access memory (RAM) is configured into two ways, each way including tag and valid-bit storage for associatively searching a directory for cache data-array addresses. The two ways, a right way and a left way, each store tag addresses. There are two lines selected during a line fill to one of the ways. A least recently used (LRU) pointer selects which way to fill on a line fill cycle. The right way is selected for a line fill in response to right hit signal provided that the LRU pointer points to the right way. The LRU pointer is flipped to point to the left way upon the filling of the right line of the right way. The left way is selected for a line fill in response to a left hit signal provided that the LRU pointer points to the left way. The LRU pointer is flipped to point to the right way upon the filling of the left line of the left way.

Abstract: An opportunistic time-borrowing domino logic includes a domino pipeline having a plurality of logic gates coupled in series and controlled by first, second, third and fourth clock signals. The first domino gate in a half-cycle is clocked by either the first or the second clock signals, wherein the last domino gate in a half-cycle is clocked by either the third or the fourth clock cycles. The second clock signal is an inverse of the first clock signal, and the third and fourth clock signals have local delayed clock phases in which the falling edges of the third and fourth clock signals are delayed relative to the falling edges of the respective first and second clock signals. In a first half-cycle, a first type of domino gate is controlled by the first clock signal, with subsequent domino gates of the same type being controlled by the third clock signal.

Abstract: A cache circuit for a computer microprocessor and a method for performing cache operations (e.g., read and write) in a single, short cycle using overlapped clocking. The cache includes a tag array, a status array, and a data array. Parity information is generated and checked to verify data and tag integrity. The parity field is stored in a status array physically separate from the tag array. The status array is offset in timing so that it lags behind the tag array for both read and write operations. Therefore, fields in the status array can be written in the early part of the next clock cycle without affecting the tag array or another operation that may be scheduled for the next time cycle.

Abstract: A set select circuit and method for selecting a set in a set associative cache in a microprocessor. The set select circuit, responsive to a main clock, includes an input latch coupled to receive select data before the main clock cycle. The input latch is transparent to set select data so that predecoding can begin before the main clock. The input latch latches the set select data on the initial clock edge and holds the set select data during the first half of the main clock cycle. A pre-decoder is coupled to the input latch for receiving and predecoding the set select data, and a decoder is coupled to the predecoder for receiving and decoding the pre-decoded set select data to supply an output to an output latch. The output latch is also coupled to a clock inverter to receive the inverted delayed clock signal. The output latch is transparent during the second half of an inverted delayed clock cycle.

Abstract: A processor communicates over a memory bus with a main memory and a cache by asserting an address strobe signal (ADS) to initiate a memory access. The cache includes a cache controller and a tag random access memory (tag RAM). Internal cycles are tracked by a first logic in the tag RAM that responds to an external cycle (EXCYC) signal and asserts an internal cycle (INCYC) signal during a time when a request to the tag RAM is pending. A second logic combines the INCYC signal with the. ADS to generate an address strobe wait (ADSWAIT) signal. A third logic combines the ADSWAIT signal with the ADS to generate an address strobe cycle (ADSCYC) signal. A fourth logic responsive to one of several end-of-cycle signals generates a terminate signal to signify an end of a current cycle. A fifth logic asserts the EXCYC signal in response to the ADSCYC signal and unasserts the EXCYC signal in response to the terminate signal.

Abstract: A cache controller tag ram is configured into a two ways, each way including tag and valid-bit storage for associatively searching the directory for cache data-array addresses. The two ways, a right way and a left way, each store tag addresses. First means are provided for asserting a flush signal upon the condition that a warm start reset is recognized or a power up condition is recognized. Logic causes all pending write requests to be withdrawn in response to the flush signal. The directory is cleared by setting all valid, write protect and least recently used (LRU) bits to zero in both of the ways. Subsequent write requests use a line fill algorithm to ensure that correct data is written into the directory by choosing which way to select for a line fill after the bits have been cleared.

Abstract: A cache controller sits in parallel with a microprocessor bus and includes a tag RAM for associatively searching a directory for cache data-array addresses. Two normal address latches are provided to capture a cycle address in case the current cycle is extended by a pending tag RAM access. At any time, except when the next cycle has started, but during which the current cycle is in progress, one latch is open to an input buffer such that the input address is latched by that latch. The other latch holds the current cycle address until the cycle ends. The current cycle can be extended with snoops. The current cycle address has to be maintained as long as the cycle is still in progress. In the meantime, the external cycle might have ended and a next cycle started. The second address latch is used to capture the address corresponding to this new cycle. As signal selects which of the two latches will supply the address via a MUX to the tag RAM.

Abstract: A cache controller (10) which sits in parallel with a microprocessor bus (14, 15, 29) so as not to impede system response in the event of a cache miss. The cache controller tagram (24) is configured into a two ways, each way including tag and valid-bit storage for associatively searching the directory for cache data-array addresses. The external cache memory (8) is organized such that both ways are simultaneously available to a number of available memory modules in the system to thereby allow the way access time to occur in parallel with the tag lookup.

Abstract: Arbitration of a system bus shared by a plurality of digital processors, input and output devices and memories may be shared in an intelligent and efficient manner by using an arbitration method and an arbiter and bus controller circuit which allows a lower priority processor or user to access the system bus during those times in which a higher priority user of the system bus is not actively accessing the system bus. Thus, without altering the priority assignments among multiple users of a system bus, lower priority users requesting access may be allowed selective and limited access to the system bus during those times in which a higher priority user is in either an idle or halt state or is engaged in utilizing another bus, such as an input/output bus or resident bus.