Abstract: A test pattern syntax allows cycles of interest for a device to be tagged as serial protocol data sources during test of the integrated circuit in semiconductor automatic test equipment (ATE). A test pattern syntax is used to tag serial bits of interest. Metadata (from serial capture control contents) in combination with the tagged serial bits of interest received during the test of the integrated circuit is used to identify data in the tagged serial bits of interest. Data in the with tagged serial bits of interest is sent to other location(s) in the automated test equipment. The data in the tagged serial bits of interest can be used for real time decisions (such as thermal control) or plotted in a Graphical user interface (GUI) during test of the integrated circuit.

Abstract: The disclosure is directed to a device interface, system and method for connecting a Tester Interface Unit (TIU) to an automated test equipment that enable data rates of over 1.0 Gbps over scalable high speed cables. The device interface includes at least one flange assembly connecting an electron beam probe (EBP) in a vacuum-controlled environment to an ambient environment, the flange assembly including a vacuum-controlled passthrough environment coupled to the EBP, a plurality of cables coupled to a plurality of connectors within the vacuum-controlled passthrough environment to provide power, control and signal connections to the ambient environment, the plurality cables including plurality of hermetically-sealed printed circuit boards (PCBs) carrying digital high speed signals from the TIU, a plurality of power cables supporting a plurality of power requirements, and a plurality of ATE communication control cables to direct the TIU.

Abstract: Embodiments described herein may be directed to receiving a plurality of data captured, respectively, by a plurality of test instruments coupled to a device under test, wherein a plurality of data elements within, respectively, the plurality of captured data are associated with a timestamp based upon a time a data element was captured. Embodiments may also analyze the received plurality of data captured, respectively, by the one or more test instruments, and graphically display at least a portion of the analyzed plurality of captured data to a user. Other embodiments may be identified herein.

Abstract: Embodiments herein relate to apparatus, systems, and methods to compress a test pattern onto a field programmable gate array to test a device under test. This may include identifying values of a plurality of drive pins for a plurality of test cycles to apply to an input of the DUT for each of the plurality of test cycles, identifying values of a plurality of compare pins for the plurality of test cycles to compare an output of the DUT, respectively, for each of the plurality of test cycles, analyzing the identified values, compressing, based on the analysis, the values of the plurality of drive pins and the plurality of compare pins, and storing the compressed values on the FPGA.

Abstract: Embodiments described herein may be directed to receiving a plurality of data captured, respectively, by a plurality of test instruments coupled to a device under test, wherein a plurality of data elements within, respectively, the plurality of captured data are associated with a timestamp based upon a time a data element was captured. Embodiments may also analyze the received plurality of data captured, respectively, by the one or more test instruments, and graphically display at least a portion of the analyzed plurality of captured data to a user. Other embodiments may be identified herein.

Abstract: Embodiments herein relate to apparatus, systems, and methods to compress a test pattern onto a field programmable gate array to test a device under test. This may include identifying values of a plurality of drive pins for a plurality of test cycles to apply to an input of the DUT for each of the plurality of test cycles, identifying values of a plurality of compare pins for the plurality of test cycles to compare an output of the DUT, respectively, for each of the plurality of test cycles, analyzing the identified values, compressing, based on the analysis, the values of the plurality of drive pins and the plurality of compare pins, and storing the compressed values on the FPGA.

Abstract: Techniques and configurations are disclosed herein for communication between devices. In some embodiments, a bus for communication between first and second devices may include a transmit buffer and one or more processing devices. The one or more processing devices may be configured to receive first asynchronous data from an operating system, running on a central processing unit of the first device, on an operating system signal path; transmit the first asynchronous data from the first device to the second device on a command signal path; transmit first data from the transmit buffer to the second device at a first fixed packet frequency on a transmit signal path; and receive data from the second device at a second fixed packet frequency on a receive signal path different from the transmit signal path. Other embodiments may be disclosed and/or claimed.

Abstract: Techniques and configurations are disclosed herein for communication between devices. In some embodiments, a bus for communication between first and second devices may include a transmit buffer and one or more processing devices. The one or more processing devices may be configured to receive first asynchronous data from an operating system, running on a central processing unit of the first device, on an operating system signal path; transmit the first asynchronous data from the first device to the second device on a command signal path; transmit first data from the transmit buffer to the second device at a first fixed packet frequency on a transmit signal path; and receive data from the second device at a second fixed packet frequency on a receive signal path different from the transmit signal path. Other embodiments may be disclosed and/or claimed.

Abstract: Embodiments of a thermal compression bonding process bond head and a method for producing a thermal compression bonding process bond head are disclosed. In some embodiments, the bond head includes a thermal compression bonding process heater and a cooling block coupled to the heater through an annular structure. The annular structure surrounds a lower portion of the cooling block and couples the cooling block to the heater such that there is no direct mechanical contact between the cooling block and the heater.

Abstract: A method is described that includes configuring multiple test units of a semiconductor device tester with respective information indicating respective storage space within either or both of an off load processing unit and central control unit of the tester. The method further includes streaming DUT data from the test units to their respective storage space within at least one of the off load processing unit and the central control unit such that the test units continually initiate the sending of their respective DUT data to their respective storage space.

Abstract: Techniques and configurations are disclosed herein for communication between devices. In some embodiments, a bus for communication between first and second devices may include a transmit buffer and one or more processing devices. The one or more processing devices may be configured to receive first asynchronous data from an operating system, running on a central processing unit of the first device, on an operating system signal path; transmit the first asynchronous data from the first device to the second device on a command signal path; transmit first data from the transmit buffer to the second device at a first fixed packet frequency on a transmit signal path; and receive data from the second device at a second fixed packet frequency on a receive signal path different from the transmit signal path. Other embodiments may be disclosed and/or claimed.

Abstract: Embodiments of a thermal compression bonding process bond head and a method for producing a thermal compression bonding process bond head are disclosed. In some embodiments, the bond head includes a thermal compression bonding process heater and a cooling block coupled to the heater through an annular structure. The annular structure surrounds a lower portion of the cooling block and couples the cooling block to the heater such that there is no direct mechanical contact between the cooling block and the heater.

Abstract: Techniques and configurations are disclosed herein for communication between devices. In some embodiments, a bus for communication between first and second devices may include a transmit buffer and one or more processing devices. The one or more processing devices may be configured to receive first asynchronous data from an operating system, running on a central processing unit of the first device, on an operating system signal path; transmit the first asynchronous data from the first device to the second device on a command signal path; transmit first data from the transmit buffer to the second device at a first fixed packet frequency on a transmit signal path; and receive data from the second device at a second fixed packet frequency on a receive signal path different from the transmit signal path. Other embodiments may be disclosed and/or claimed.

Abstract: A connector assembly is disclosed and claimed. The connector assembly includes a connector and a cable attachable at one end to the connector. The cable includes a first conductive layer and a second conductive layer disposed over the first conductive layer. A layer of insulation material is disposed at least between the first conductive layer and the second conductive layer and a plurality of capacitors are connected between the first conductive layer and the second conductive layer.

Abstract: A connector assembly is disclosed and claimed. The connector assembly includes a connector and a cable attachable at one end to the connector. The cable includes a first conductive layer and a second conductive layer disposed over the first conductive layer. A layer of insulation material is disposed at least between the first conductive layer and the second conductive layer and a plurality of capacitors are connected between the first conductive layer and the second conductive layer.

Abstract: A connector assembly is disclosed and claimed. The connector assembly includes a connector and a cable attachable at one end to the connector. The cable includes a first conductive layer and a second conductive layer disposed over the first conductive layer. A layer of insulation material is disposed at least between the first conductive layer and the second conductive layer and a plurality of capacitors are connected between the first conductive layer and the second conductive layer.