Abstract: A bus bridge mechanism is provided with an automatic delayed transaction enable mode. When the automatic delayed transaction enable mode is activated, a bus master making a read request is immediately signaled to retry the transaction, and the read request is treated by the bus bridge as a delayed read request to be completed asynchronously. The delayed read request, when completed, supplies data to the bus master on the next retry of the read request by the bus master following the completion of the delayed read request.

Abstract: A flexible address mapping method and mechanism allows mapping regions of a microcontroller's memory and I/O address spaces for a variety of applications by defining memory regions which are mapped to one of a set of physical devices by a programmable address mapper controlled by a set of programmable address registers. The mapping allows setting attributes for a memory region to prohibit writes, caching, and code execution. A deterministic priority scheme allows memory regions to overlap, mapping addresses in overlapping regions to the device specified by the highest priority programmable address register.

Abstract: A microcontroller provides a flexible architecture to readily support both general embedded applications and communications applications. The microcontroller includes an embedded processor, a relatively low-speed general purpose peripheral bus controller, a relatively high-speed peripheral bus host bridge, a primary memory controller, and a secondary memory controller, each coupled to a processor bus. The general purpose peripheral bus controller is coupled to a relatively low-speed general purpose peripheral bus which is coupled to a plurality of integrated general purpose peripherals. The relatively high-speed peripheral bus host bridge is coupled to a relatively high-speed peripheral bus capable of supporting a plurality of communication-oriented peripherals. The secondary memory controller shares an address bus with the general purpose peripheral bus controller and shares a data bus with either the primary memory controller or the general purpose peripheral bus controller.

Abstract: A microcontroller for PC/AT-compatible or non-PC/AT compatible embedded environments is disclosed. The microcontroller includes a general purpose bus which may emulate an ISA bus in a PC/AT-compatible mode. PC/AT-compatible DMA channels, interrupt controllers, programmable timers, a real-time clock, processor, and a flexible memory and an I/O mapping scheme are provided by the microcontroller. The programmable timers, interrupt controllers, DMA channels and I/O mapping can be configured for a PC/AT-compatible mode or a non-PC/AT-compatible mode. In particular, the plurality of interrupt controllers are configured such that some are enabled during PC/AT-compatible operation while the remainder are disabled. The microcontroller further embeds several PC/AT peripheral devices and yet maintains the flexibility to support external devices if desired by the embedded system designer. Other PC/AT-compatible features are also supported by the microcontroller.

Abstract: One disclosed embodiment of the present invention provides a technique for serializing a parallel peripheral bus within a microcontroller. The technique is implemented by converting the parallel data, address, and control information on the parallel peripheral bus to a serial data stream. The serial data stream is then transmitted to an external device. Another embodiment of the present invention provides a technique for receiving a serial data stream from an external device and converting the serial data stream to parallel data, address and control information. The parallel information is then transmitted to the embedded system on the parallel peripheral bus.

Abstract: A processor-based system such as a microcontroller supports a non-concurrent mode in which a bus master requesting ownership of a peripheral bus is forced to acquire ownership of both the peripheral bus and a processor bus. The system includes a peripheral bus arbiter to detect a peripheral bus request for the peripheral bus by a bus master, to generate a processor bus request for the processor bus in response to detecting the peripheral bus request, and to grant the bus master ownership of the peripheral bus if the bus master is granted ownership of the processor bus. The peripheral bus arbiter maintains ownership of the processor bus by the bus master until the bus master releases ownership of the peripheral bus. Similarly, a bus master seeking ownership of the processor bus can be forced to acquire ownership of the peripheral bus. The non-concurrent mode can be applied to various multi-bus architectures. One advantage of the non-concurrent mode is improved debug capability.

Abstract: A communication system is provided that includes a mechanism for selectively addressing memory banks depending upon the configuration of that system. The communication system can therefore operate in accordance with two possible modes of operation. According to a first mode, the local CPU can access one set of memory banks concurrent with an external device accessing the other set of memory banks. According to a second mode of operation, either the local CPU can access the memory banks or an external device can access the memory banks, one exclusive of the other. In one version of the second mode of operation, address signals to the memory banks can be physically connected leaving signals free to be used as general purpose input/output signals. The mechanism by which memory banks can be addressed and data transferred to and from those banks readily lends itself to communication applications to which the present system may be attributed.

Abstract: A DRAM control circuit accommodates different speed grade DRAMs by modifying the RAS strobe. A number of wait states are inserted into a DRAM access cycle, having a start time and an end time, between the start and the end time of the access cycle. When the number of wait states inserted is zero, the RAS is deasserted at a first time relative to the end of the access cycle. When the number of wait states is at least one, the RAS is deasserted at a second time, earlier than the first time, relative to the end time of the access cycle, thereby increasing the row address strobe precharge time.