Abstract: A selective memory addressing scheme employs a programmable read only memory (PROM) which responds to the opcode of the next instruction to be executed and supplies control information to memory module selection registers.The memory module selection registers operate in conjunction with the internal address registers to provide the necessary steering information for properly addressing the intended memory location. The PROM is programmed in accordance with the instruction set by which the processor operates and is coupled to decode the opcode contents of the instruction register that has been loaded, in a lookahead fashion, with the instruction following the instruction presently being executed by the central processing unit.The PROM has a first output that defines whether or not a second output of the PROM is to be used to select the memory module containing the operand to be referenced in the execution of the next instruction.

Abstract: A microprogrammed controller for interconnection between a central processor unit and at least one peripheral unit for controlling the transfer of data therebetween in response to instructions from the central processor unit provides for simplified bit manipulation through a feedback circuit which feeds the data to be supplied to the peripheral unit back to the input bus of the controller for further processing. In this way bit manipulation can be accomplished with a single microinstruction to provide for higher speed and efficiency of operation.