Abstract: A method and system is provided for avoiding data bus contention between EDO DRAM banks during a burst cycle to a memory page crossing a memory bank boundary. Each memory bank has output drivers configured to selectively drive data on a common data bus. The disclosed method and system contemplate decoding memory addresses into bank select signals and comparing the bank select signals for the current memory cycle to the state of the bank select signals in the previous cycle. If the current access is to a different bank, then the cycle is delayed and a disable signal is pulsed active to the EDO DRAM, disabling the output drivers. The memory page is kept open in the memory banks to allow bursts across bank boundaries. The current cycle is then allowed to continue to completion and data bus contention is avoiding while crossing the bank boundary.

Abstract: A computer system is provided including a CPU, a graphics controller, system memory, data steering logic, a DMA controller and arbitration logic. The graphics controller and system memory are coupled to a high-speed data bus. Data accessed by the CPU, the DMA controller and the graphics controller is all stored in the system memory. The data steering logic is also coupled to the high-speed data bus and to a low-speed data bus, and to the CPU. The data steering logic is configured to selectively couple the CPU to either the high-speed data bus or the low-speed data bus, thereby accommodating data transfers between the CPU and a bus device connected to the slow-speed data bus concurrent with data transfers between the graphics controller and the system memory. The data steering logic may also accommodate data transfers by the DMA controller on the slow-speed data bus concurrent with graphics controller data transfers.