Abstract: Processor circuitry is disclosed for setting a memory address register to a predetermined address upon the receipt of an interrupt request. The receipt of the request extends a steady state signal through an AND gate to the input of the counter to hardwire jam it to a predetermined address which defines the memory location of the first word of a subroutine associated with the request. The jam signal remains on the register input until the addressed memory location is read out. A readout of this location disables the AND gate and removes the jam signal from the counter. The AND gate is restored to normal when the last word of the subroutine is read out to permit new interrupt requests to be honored. The continuous application of the jam signal to the register until the addressed location is read out increases the probability of the register being successfully set to the correct address.

Abstract: A processor is disclosed having improved circuitry for (1) generating m+n-bit address words from n-bit data words and (2) converting m+n-bit address words back into data words having an n-bit format. The processor includes a first arithmetic unit (AMU) that is n bits wide and which receives n-bit words from a data bus. The processor further includes a second AMU that is m bits wide and which is connected to receive the m least significant bits of an n-bit word stored in the first AMU.

Abstract: An electronic key telephone system is disclosed in which connections among the station sets and telephone lines are made in a central time division switching network remote from the station sets. Each station set and line is equipped with a port circuit having an individual shift register for defining the time slot interval during which a connection may take place. To assign a time slot to a port circuit, the main controller interrogates the network to find an idle time slot and then furnishes that time slot number to the network controller. In order to save central memory and to increase system reliability, the main activity memory which stores an indication of which ports are or should be interconnected in the network need not contain any reference to the time slot number assigned for the particular connection. In order periodically to verify that actual network connections reflect the state of the activity memory, two types of audits are performed.