Patents by Inventor James P. Crowley

James P. Crowley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11899948
    Abstract: Methods, systems, and devices for performance control for a memory sub-system are described. A memory sub-system can monitor a backend for writing data to a memory device. The memory sub-system can determine that the bandwidth of the backend satisfies one or more performance criteria that are based on performance between the memory sub-system and a host system. In some embodiments, the memory sub-system can allocate a quantity of slots of a buffer to a frontend of the memory sub-system based on determining that the bandwidth of the backend satisfies the one or more performance criteria. Slots of the buffer can be configured to receive data from the frontend for writing to the memory device by the backend.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: February 13, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Yun Li, James P. Crowley, Jiangang Wu, Peng Xu
  • Patent number: 11756626
    Abstract: Methods, systems, and devices for memory die resource management are described. A resource manager can determine, from a set of global resources for multiple memory dies of a memory sub-system, a set of die-specific resources for a memory die of the multiple memory dies of the memory sub-system. In some case, the set of die-specific resources can be allocated for read commands for the memory die. The resource manager can assign a read command to a die-specific resource of the set of die-specific resources based on the die-specific resource being available and refrain from assigning the read command to the die-specific resource based on the die-specific resource being unavailable.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: September 12, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Jiangang Wu, James P. Crowley, Yun Li
  • Patent number: 11709732
    Abstract: A die read counter and a block read counter are maintained for a specified block of a memory device. An estimated number of read events associated with the specified block is determined based on a value of the block read counter and a value of the die read counter. Responsive to determining that the estimated number of read events satisfies a criterion, a media management operation of one or more pages associated with the specified block is performed.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: July 25, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Gerald L. Cadloni, Mark Ish, James P. Crowley
  • Publication number: 20230071878
    Abstract: Methods, systems, and devices for performance control for a memory sub-system are described. A memory sub-system can monitor a backend for writing data to a memory device. The memory sub-system can determine that the bandwidth of the backend satisfies one or more performance criteria that are based on performance between the memory sub-system and a host system. In some embodiments, the memory sub-system can allocate a quantity of slots of a buffer to a frontend of the memory sub-system based on determining that the bandwidth of the backend satisfies the one or more performance criteria. Slots of the buffer can be configured to receive data from the frontend for writing to the memory device by the backend.
    Type: Application
    Filed: November 9, 2022
    Publication date: March 9, 2023
    Inventors: Yun Li, James P. Crowley, Jiangang Wu, Peng Xu
  • Publication number: 20220413719
    Abstract: Methods, systems, and devices for data stream processing for maintaining queues for memory sub-systems are described. A number of commands included in a queue of a plurality of queues of a memory die of a memory sub-system can be determined. Each queue can be associated with a respective priority level and can be configured to maintain a respective set of commands. A command can be assigned to the queue based on a number of commands included in the queue. One or more commands can be issued from the queues based on the respective priority levels of the queues.
    Type: Application
    Filed: March 10, 2020
    Publication date: December 29, 2022
    Inventors: Jiangang Wu, Jing Sang Liu, James P. Crowley, Yun Li
  • Publication number: 20220404979
    Abstract: Methods, systems, and devices for managing queues of a memory sub-system are described. A first command can be assigned to a first queue of a memory die of a memory sub-system. The first queue can be is associated with a first priority level and the memory die can include a second queue associated with a second priority level different from the first priority level. The second queue can include a second command, where the first command and the second command are each associated with a respective operation to be performed on the memory sub-system. In some examples, the first command can be issued before the second command based on the first and second priority levels.
    Type: Application
    Filed: March 10, 2020
    Publication date: December 22, 2022
    Inventors: Jiangang Wu, Jing Sang Liu, Yun Li, James P. Crowley
  • Patent number: 11520502
    Abstract: Methods, systems, and devices for performance control for a memory sub-system are described. A memory sub-system can monitor a backend for writing data to a memory device. The memory sub-system can determine that the bandwidth of the backend satisfies one or more performance criteria that are based on performance between the memory sub-system and a host system. In some embodiments, the memory sub-system can allocate a quantity of slots of a buffer to a frontend of the memory sub-system based on determining that the bandwidth of the backend satisfies the one or more performance criteria. Slots of the buffer can be configured to receive data from the frontend for writing to the memory device by the backend.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: December 6, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Yun Li, James P. Crowley, Jiangang Wu, Peng Xu
  • Patent number: 11520487
    Abstract: Exemplary methods, apparatuses, and systems include a memory controller detecting that an asynchronous power loss event has occurred. Upon determining that a write operation is in progress to a first type of non-volatile memory element, the memory controller cancels the write operation and retrieves data associated with the write operation. The memory controller sends a request for a second physical address pointing to a second type of non-volatile memory element. Upon receiving a second physical address corresponding to a logical address, the memory controller stores the data at the second physical address.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: December 6, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Michael W. Sheperek, James P. Crowley
  • Publication number: 20220291995
    Abstract: A die read counter and a block read counter are maintained for a specified block of a memory device. An estimated number of read events associated with the specified block is determined based on a value of the block read counter and a value of the die read counter. Responsive to determining that the estimated number of read events satisfies a criterion, a media management operation of one or more pages associated with the specified block is performed.
    Type: Application
    Filed: June 2, 2022
    Publication date: September 15, 2022
    Inventors: Gerald L. Cadloni, Mark Ish, James P. Crowley
  • Publication number: 20220237078
    Abstract: A total read counter, a plurality of die read counters, and a plurality of block read counters are maintained. Each die read counter is associated with a respective die of a memory device. A value of a block read counter and a value of a die read counter are determined for a specified block. Based on the value of the block read counter, the value of the die read counter, and the value of the total read counter, an estimated number of read events associated with the specified block of the memory device is determined. Responsive to determining that the estimated number of read events satisfies a predefined criterion, a media management operation of one or more pages associated with the specified block is performed.
    Type: Application
    Filed: January 27, 2021
    Publication date: July 28, 2022
    Inventors: Gerald L. Cadloni, Mark Ish, James P. Crowley
  • Patent number: 11379304
    Abstract: A total read counter, a plurality of die read counters, and a plurality of block read counters are maintained. Each die read counter is associated with a respective die of a memory device. A value of a block read counter and a value of a die read counter are determined for a specified block. Based on the value of the block read counter, the value of the die read counter, and the value of the total read counter, an estimated number of read events associated with the specified block of the memory device is determined. Responsive to determining that the estimated number of read events satisfies a predefined criterion, a media management operation of one or more pages associated with the specified block is performed.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: July 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Gerald L. Cadloni, Mark Ish, James P. Crowley
  • Publication number: 20220059169
    Abstract: Methods, systems, and devices for memory die resource management are described. A resource manager can determine, from a set of global resources for multiple memory dies of a memory sub-system, a set of die-specific resources for a memory die of the multiple memory dies of the memory sub-system. In some case, the set of die-specific resources can be allocated for read commands for the memory die. The resource manager can assign a read command to a die-specific resource of the set of die-specific resources based on the die-specific resource being available and refrain from assigning the read command to the die-specific resource based on the die-specific resource being unavailable.
    Type: Application
    Filed: November 5, 2021
    Publication date: February 24, 2022
    Inventors: Jiangang Wu, James P. Crowley, Yun Li
  • Patent number: 11210154
    Abstract: Feedback relating to errors in memory operations on a plurality of memory cells is received by a memory sub-system. At least one processing level corresponding to a program distribution is updated based on the feedback to adjust an error measure between pages of the plurality of memory cells and to adjust a read window budget within a page of the plurality of cells. The updating of the at least one processing level is based on information for the at least one processing level that is stored in a data-structure.
    Type: Grant
    Filed: November 21, 2020
    Date of Patent: December 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Michael Sheperek, Bruce A. Liikanen, Larry J. Koudele, James P. Crowley, Stuart A. Bell
  • Patent number: 11189347
    Abstract: Methods, systems, and devices for memory die resource management are described. A resource manager can determine, from a set of global resources for multiple memory dies of a memory sub-system, a set of die-specific resources for a memory die of the multiple memory dies of the memory sub-system. In some case, the set of die-specific resources can be allocated for read commands for the memory die. The resource manager can assign a read command to a die-specific resource of the set of die-specific resources based on the die-specific resource being available and refrain from assigning the read command to the die-specific resource based on the die-specific resource being unavailable.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: November 30, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jiangang Wu, James P. Crowley, Yun Li
  • Publication number: 20210303340
    Abstract: Methods, systems, and devices for a read counter for quality of service design are described. First commands may be assigned to a first queue of a memory die of a memory sub-system, wherein the first queue is associated with a first priority level. The memory die may include a second queue associated with a second priority level different from the first priority level, the second queue comprising one or more second commands assigned. Based at least in part on a counter associated with the first queue and the first and second priority levels, it may be determined that a threshold number of the first commands of the first queue have issued without a command from the one or more second commands having issued. A command from the second commands may issue before issuing a next command of the first commands based at least in part on the counter.
    Type: Application
    Filed: March 24, 2020
    Publication date: September 30, 2021
    Inventors: Yun Li, Jiangang Wu, James P. Crowley
  • Publication number: 20210287750
    Abstract: Methods, systems, and devices for memory die resource management are described. A resource manager can determine, from a set of global resources for multiple memory dies of a memory sub-system, a set of die-specific resources for a memory die of the multiple memory dies of the memory sub-system. In some case, the set of die-specific resources can be allocated for read commands for the memory die. The resource manager can assign a read command to a die-specific resource of the set of die-specific resources based on the die-specific resource being available and refrain from assigning the read command to the die-specific resource based on the die-specific resource being unavailable.
    Type: Application
    Filed: March 13, 2020
    Publication date: September 16, 2021
    Inventors: Jiangang Wu, James P. Crowley, Yun Li
  • Publication number: 20210200453
    Abstract: Methods, systems, and devices for performance control for a memory sub-system are described. A memory sub-system can monitor a backend for writing data to a memory device. The memory sub-system can determine that the bandwidth of the backend satisfies one or more performance criteria that are based on performance between the memory sub-system and a host system. In some embodiments, the memory sub-system can allocate a quantity of slots of a buffer to a frontend of the memory sub-system based on determining that the bandwidth of the backend satisfies the one or more performance criteria. Slots of the buffer can be configured to receive data from the frontend for writing to the memory device by the backend.
    Type: Application
    Filed: December 31, 2019
    Publication date: July 1, 2021
    Inventors: Yun Li, James P. Crowley, Jiangang Wu, Peng Xu
  • Publication number: 20210073061
    Abstract: Feedback relating to errors in memory operations on a plurality of memory cells is received by a memory sub-system. At least one processing level corresponding to a program distribution is updated based on the feedback to adjust an error measure between pages of the plurality of memory cells and to adjust a read window budget within a page of the plurality of cells. The updating of the at least one processing level is based on information for the at least one processing level that is stored in a data-structure.
    Type: Application
    Filed: November 21, 2020
    Publication date: March 11, 2021
    Inventors: Michael Sheperek, Bruce A. Liikanen, Larry J. Koudele, James P. Crowley, Stuart A. Bell
  • Patent number: 10877832
    Abstract: Feedback relating to errors in memory operations on a plurality of memory cells is received by a memory sub-system. At least one processing level corresponding to a program distribution is updated based on the feedback to adjust an error measure between pages of the plurality of memory cells and to adjust a read window budget within a page of the plurality of cells. The updating of the at least one processing level is based on information for the at least one processing level that is stored in a data-structure.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Michael Sheperek, Bruce A. Liikanen, Larry J. Koudele, James P. Crowley, Stuart A. Bell
  • Patent number: 10872039
    Abstract: A controller selects a redundancy context for eviction in response to a request for a redundancy context. The redundancy context includes buffer data and an identifier. The redundancy context is evicted by instructing a redundancy component to send the buffer data and identifier to a memory component to store in a buffer as an evicted context. The controller instructs the memory component to provide the evicted context for storage in a controller buffer. A new redundancy context is allocated to the requester following the eviction.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: December 22, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: James P. Crowley, Yuriy Pavlenko, Karl D. Schuh