Patents by Inventor James P. Kimball

James P. Kimball has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6864141
    Abstract: A method of making a thin gate dielectric includes providing a metal silicate on a silicon substrate. Nitrogen is implanted into the metal silicate.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: March 8, 2005
    Assignee: LSI Logic Corporation
    Inventors: Wai Lo, James P. Kimball, Verne C. Hornback
  • Patent number: 6849512
    Abstract: A method of making a thin gate dielectric includes implanting a barrier substance into a region of a silicon substrate. A capacitance-increasing material is implanted into the silicon substrate. An outside layer of the silicon substrate is oxidized to form a first silicon oxide layer. The silicon substrate is oxidized between the first silicon oxide layer and the region.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: February 1, 2005
    Assignee: LSI Logic Corporation
    Inventors: Wai Lo, James P. Kimball, Verne C. Hornback
  • Patent number: 6759337
    Abstract: A process for etching oxide is disclosed wherein a reproducibly accurate and uniform amount of silicon oxide can be removed from a surface of an oxide previously formed over a semiconductor substrate by exposing the oxide to a nitrogen plasma in an etch chamber while applying an rf bias to a substrate support on which the substrate is supported in the etch chamber. The thickness of the oxide removed in a given period of time may be changed by changing the amount of rf bias applied to the substrate through the substrate support.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: July 6, 2004
    Assignee: LSI Logic Corporation
    Inventors: Sheldon Aronowitz, Valeriy Sukharev, John Haywood, James P. Kimball, Helmut Puchner, Ravindra Manohar Kapre, Nicholas Eib
  • Patent number: 6413881
    Abstract: A process for inhibiting the passage of dopant from a gate electrode into a thin gate oxide comprises nitridation of the upper surface of the thin gate oxide, prior to formation of the gate electrode over the gate oxide, to thereby form a barrier of nitrogen atoms in the upper surface region of the gate oxide adjacent the interface between the gate oxide and the gate electrode to inhibit passage of dopant atoms from the gate electrode into the thin gate oxide during annealing of the structure. In one embodiment, a selective portion of silicon oxide on a silicon substrate may be etched to thin the oxide to the desired thickness using a nitrogen plasma with a bias applied to the silicon substrate. Nitridation of the surface of the etched silicon oxide is then carried out in the same apparatus by removing the bias from the silicon substrate.
    Type: Grant
    Filed: March 9, 2000
    Date of Patent: July 2, 2002
    Assignee: LSI Logic Corporation
    Inventors: Sheldon Aronowitz, John Haywood, James P. Kimball, Helmut Puchner, Ravindra Manohar Kapre, Nicholas Eib
  • Patent number: 6331468
    Abstract: A process is described for using a silicon layer as an implant and out-diffusion layer, for forming defect-free source/drain regions in a semiconductor substrate, and also for subsequent formation of silicon nitride spacers. A nitrogen-containing dopant barrier layer is first formed over a single crystal semiconductor substrate by nitridating either a previously formed gate oxide layer, or a silicon layer formed over the gate oxide layer, to form a barrier layer comprising either a silicon, oxygen, and nitrogen compound or a compound of silicon and nitrogen. The nitridating may be carried out using a nitrogen plasma followed by an anneal. A polysilicon gate electrode is then formed over this barrier layer, and the exposed portions of the barrier layer remaining are removed. An amorphous silicon layer of predetermined thickness is then formed over the substrate and polysilicon gate electrode.
    Type: Grant
    Filed: May 11, 1998
    Date of Patent: December 18, 2001
    Assignee: LSI Logic Corporation
    Inventors: Sheldon Aronowitz, Helmut Puchner, Ravindra A. Kapre, James P. Kimball
  • Patent number: 6060375
    Abstract: A crystalline semiconductor gate electrode having a re-entrant geometry and a process for making same are disclosed. The novel gate electrode may be formed from a polysilicon layer on a substrate by first implanting a masked polysilicon layer with a neutral species, i.e., a species which will not introduce a dopant into the polysilicon, such as a Group IV element, e.g., silicon, or a Group VIII element, e.g., argon. The neutral species is implanted into the masked polysilicon layer at an angle to provide a tapered implanted region which undercuts one side of the length (long dimension) of the mask. The substrate may then be rotated 180.degree. and then again implanted to provide a tapered implanted region which undercuts the opposite side of the length of the mask. When gate electrodes with such re-entrant geometry are to be formed on a substrate with their long axes at right angles to one another, i.e.
    Type: Grant
    Filed: July 31, 1996
    Date of Patent: May 9, 2000
    Assignee: LSI Logic Corporation
    Inventors: Jon Owyang, Sheldon Aronowitz, James P. Kimball