Patents by Inventor James P. Libous

James P. Libous has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6584606
    Abstract: A method of analyzing I/O cell layouts for integrated circuits, such as ASICs, includes defining a proposed I/O cell layout on a selected chip image, providing a set of limit rules for electromigration, IR voltage drop and di/dt noise for the selected chip image, providing characteristics for each I/O cell type used in the proposed I/O cell layout, checking the proposed I/O cell layout by applying the limit rules to the proposed I/O cell layout and reporting all I/O cells used in the proposed I/O cell layout that do not meet the limit rules for the selected chip image.
    Type: Grant
    Filed: June 1, 2000
    Date of Patent: June 24, 2003
    Assignee: International Business Machines Corporation
    Inventors: Charles S. Chiu, James P. Libous, Rory D. Loughran, Joseph Natonio, Robert A. Proctor, Gulsun Yasar
  • Patent number: 6335494
    Abstract: Power layers of a multi-layer connection structure forming a power distribution network are partitioned to accommodate all necessary voltages for one or more chips connected thereto in each power layer. By doing so, and rearranging vias as permitted by such partitioning via length is reduced while via numbers can be increased to reduce self-inductance of the structure. Transmission lines formed by conductors in the signal layers are referenced to the correct power supply and return/image currents are made of similar path length and substantially symmetrical for both positive- and negative-going signal transitions. These effects reduce delta-I noise to levels which preserve good signal-to-noise ratios to current and foreseeable reduced signal levels.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: January 1, 2002
    Assignee: International Business Machines Corporation
    Inventors: Roger P. Gregor, James P. Libous
  • Patent number: 6037677
    Abstract: A connection array for a chip provides a substantial increase in numbers of signal connection locations and a power distribution arrangement of improved robustness and noise immunity while accommodating multiple power supply voltages by providing pairs of sub-arrays aligned with chip edges and signal connection locations formed in columns orthogonal to a chip edge or segment of the chip perimeter. Signal connections in a column are spaced at a first pitch and columns of signal connections are spaced at a second pitch. Power connections corresponding to different power supply voltages are provided between columns of signal connections and along rows which are centered between rows of signal connections generally parallel to an edge of a chip. Power distribution layers may be formed as a mesh which extends in under the chip in alignment with power connections to the chip and beyond the perimeter of the chip, as well to provide multiple low-impedance power delivery paths to improve noise immunity.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: March 14, 2000
    Assignee: International Business Machines Corporation
    Inventors: Robert A. Gottschall, Roger P. Gregor, James P. Libous