Abstract: A semiconductor device includes gate structures laterally disposed relative to one another across the semiconductor device. The row defines a frontside of the semiconductor device and a backside of the semiconductor device opposite the frontside. A cross-coupled circuit includes a first cross-couple connection connecting two gate structures on the frontside and a second cross-couple connection connecting two gate structures on the backside.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a deep trench via in a double diffusion region between a first dummy metal gate and a second dummy metal gate; a frontside metal wire conductively connected to a top surface of the deep trench via through a frontside via; and a backside metal wire conductively connected to a bottom surface of the deep trench via through a backside via and a backside contact, where the frontside metal wire and the backside metal wire are not vertically aligned but parallel to each other, and directions of the frontside and backside metal wires are orthogonal to a length direction of the deep trench via. A method of forming the same is also provided.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a metal level that includes a metal line, the metal line includes a bottom section having a first width, a middle section having a second width, and a top section having a third width, where the second width of the middle section is narrower than the first width of the bottom section and is narrower than the third width of the top section. A method of forming the semiconductor structure is also provided.

Abstract: A semiconductor structure includes a first transistor and a second transistor vertically stacked over the first transistor. The first transistor and the second transistor have horizontally aligned cell boundaries. A first set of one or more channels of the first transistor are horizontally offset from a second set of one or more channels of the second transistor within the horizontally aligned cell boundaries.

Abstract: Semiconductor devices and methods of forming the same include a top transistor that includes a first channel and a first gate. A bottom transistor includes a second channel and a second gate that has a top surface at a same height as a top surface of the first gate. A gate barrier includes a horizontal part between the bottom transistor and the top transistor and a vertical part that extends from the horizontal part to a same height as the top surfaces of the first gate and the second gate.

Abstract: A semiconductor device includes an electrical pathway connecting a frontside of the semiconductor device to a backside of the semiconductor device. The electrical pathway includes a backside wire disposed within a backside interconnect layer. A first deep via connects to the backside wire, the first deep via extending through a front end of line (FEOL) region. A local interconnect connects to and extends transversely to the first deep via to connect the backside wire to a frontside component.

Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a device layer having a first top source/drain (S/D), a second top S/D, a first bottom S/D, and a second bottom S/D. The semiconductor structure may further include a first direct back side contact connected to the first bottom S/D, a second direct back side contact connected to the second bottom S/D, and a double via. The double via may include a first half connecting a front side of the device layer to the first direct back side contact, and a second half connecting the front side to the second direct back side contact. The double via may also include a dividing cut splitting the first half of the double via from the second half of the double via.

Abstract: A semiconductor device includes metal lines disposed in a layer. The metal lines include a first spacing and a second spacing. The second spacing is larger than a minimum pitch between the metal lines. A gapping structure is disposed within the second spacing. A second air gap is disposed adjacent to the gapping structure within the second spacing.

Abstract: A semiconductor device includes a first stacked field-effect transistor structure having a first lower field-effect transistor device and a first upper field-effect transistor device. The semiconductor device also includes a second stacked field-effect transistor structure comprising a second lower field-effect transistor device and a second upper field-effect transistor device, where at least one of: the first lower field-effect transistor device includes a different number of channel layers than the second lower field-effect transistor device; and the first upper field-effect transistor device includes a different number of channel layers than the second upper field-effect transistor device.

Abstract: Embodiments of the present disclosure include a semiconductor device having stacked transistors with a bottom transistor below a top transistor, the bottom transistor having a first bottom source/drain region and a second bottom source/drain region. A first backside contact is connected to the first bottom source/drain region and a frontside wiring. A second backside contact is connected to the second bottom source/drain region and a backside power plane. A connection via is formed through the backside power plane to connect a top source/drain region of the top transistor to a backside power rail.

Abstract: Embodiments of the present disclosure relate to a local interconnect in sequential stacking of transistors. A semiconductor structure includes a first transistor stacked under a second transistor. An interconnect layer is between the first and second transistors, the interconnect layer including a conductive via and a conductive line.

Abstract: A field effect transistor (FET) device is provided. The FET device includes an active region and a gate. The active region includes a source at a first end of the active region and a drain at a second end of the active region. The gate extends across the active region and includes at least one end extending past a corresponding edge of the active region by a sub-lithographic dimension.

Abstract: A semiconductor structure extends laterally with an interconnect on one side and another interconnect on an opposing side separated by a thickness of the semiconductor structure that extends longitudinally. The semiconductor structure includes an insulating member extending laterally, a source/drain (S/D) positioned in the insulating member between the interconnects, another S/D positioned in the insulating member between the first S/D and one of the interconnects, wherein the S/Ds laps each other laterally and are offset from each other longitudinally, and a via electrically connected to the first S/D and to the aforementioned one of the interconnects.

Abstract: Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a stacked field effect transistor (FET) including a top FET and a bottom FET. Additionally, the semiconductor structure includes a bottom source/drain (S/D) contact jumper connection within a gate cut region. The gate cut includes a liner spacer and a dielectric fill within the first liner spacer. Additionally, the bottom S/D contact jumper is within the dielectric fill. The semiconductor structure further includes a top S/D contact fly-over over a bottom S/D contact in contact with the bottom S/D contact jumper. Additionally, the semiconductor structure includes a top S/D access metal track over the bottom S/D contact, through the top S/D contact. Further, the semiconductor structure includes a recessed gate cut liner facing the top S/D contact fly-over. Additionally, the semiconductor structure includes a non-recessed gate cut liner facing a non-fly-over top S/D contact.

Abstract: A semiconductor device includes a first source/drain region connected to a back end of line (BEOL) through a first contact and a first via, and a second source/drain region connected to the BEOL through a second contact, a lateral contact, and a second via. The first via passes through the lateral contact.

Abstract: A semiconductor device includes a first source/drain region, a first contact over the first source/drain region, a second source/drain region, and a lateral contact connecting the second source/drain region to a back end of line (BEOL). Portions of the first contact are recessed, and the lateral contact overlaps with the recessed portions of the first contact. The first source/drain region is formed over the second source/drain region.

Abstract: A semiconductor device includes a substrate and a transistor positioned on the substrate. The transistor includes transistor includes a channel region, a shared gate region, and a source and drain region. The source and drain region includes a concave outer wall includes a concave outer wall. A method of manufacturing a semiconductor device includes providing a substrate and forming a plurality of transistor gate structures on the substrate. A source and drain region are formed and positioned adjacent the plurality of transistor gate structures. A concave wall is recessed into material of the source and drain region toward a centerline of the source and drain region.

Abstract: A semiconductor device includes a substrate and a plurality of stacked transistors positioned on the substrate. The transistors include a gate region and a source and drain proximate the gate region. The source and drain includes an overall region and an active region. A thickness of the active region is less than a thickness of the overall region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gate-all-around field effect transistors and methods of manufacture. The structure includes: a plurality of stacked semiconductor nanosheets over a semiconductor substrate; a plurality of gate structures surrounding the plurality of semiconductor nanosheets; a conductive material between the plurality of semiconductor nanosheets and the plurality of gate structures; an inner sidewall spacer adjacent to each of the plurality of gate structures and conductive material; and source/drain regions on opposing sides of the plurality of gate structures, separated therefrom by the inner sidewall spacer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to nanosheet transistor structures with tunable channels and inner sidewall spacers and methods of manufacture. The structure includes: a plurality of stacked semiconductor nanosheets over a semiconductor substrate; a plurality of gate structures surrounding individual nanosheets of the plurality of semiconductor nanosheets, with a lower gate structure comprising a length at least equal to a length of each remaining gate structure of the plurality of gate structures; an inner sidewall spacer adjacent each of the plurality of gate structures; and source/drain regions on opposing sides of the plurality of gate structures, separated therefrom by the inner sidewall spacer.