Patents by Inventor James P. Mazza

James P. Mazza has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11913971
    Abstract: Disclosed are a motion-sensitive field effect transistor (MSFET), a motion detection system, and a method. The MSFET includes a gate structure with a reservoir containing conductive fluid and gate electrode(s). Given position(s) of the gate electrode(s) and a fill level of the fluid within the reservoir, contact between the gate electrode(s) and the fluid depends upon the orientation the MSFET channel region relative to the top surface of the conductive fluid and the orientation of the MSFET channel region relative to the top surface of the conductive fluid depends upon position in space and/or movement of the MSFET and, particularly, position in space and/or movement of the chip on which the MSFET is formed. An electrical property of the MSFET in response to specific bias conditions varies depending on whether or not or to what extent the gate electrode(s) contact the fluid and is, thus, measurable for sensing chip motion.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: February 27, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Romain H. A. Feuillette, David C. Pritchard, Elizabeth Strehlow, James P. Mazza
  • Publication number: 20240021621
    Abstract: An integrated circuit (IC) structure includes a plurality of cell rows with each cell row including a plurality of (standard) cells. A power rail for at least one pair of adjacent cell rows is asymmetric relative to a cell boundary between adjacent cells of the at least one pair of adjacent cell rows. Embodiments of the disclosure can also include the standard cell including a plurality of transistors at a device layer, and at least a portion of an isolation area at an edge of the device layer defining a cell boundary. The standard cell also includes the power rail including a first portion within the cell boundary and a second portion outside the cell boundary. The first portion and the second portion have different heights such that the power rail is asymmetric across the cell boundary. The asymmetric power rail provides seamless integration of cell libraries having different heights.
    Type: Application
    Filed: July 15, 2022
    Publication date: January 18, 2024
    Inventors: James P. Mazza, Xuelian Zhu, Jia Zeng, JR., Navneet Jain, Mahbub Rashed
  • Publication number: 20230395675
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cross couple design for high density standard cells and methods of manufacture. The structure includes a first contact connected in a cross couple circuit to at least two gate structures, and a second contact connected to the first contact at a location which is devoid of any via connection.
    Type: Application
    Filed: June 7, 2022
    Publication date: December 7, 2023
    Inventors: James P. MAZZA, Jia ZENG, Xuelian ZHU, Mahbub RASHED, Neha NAYYAR, Collin A. TRANTER
  • Publication number: 20230335484
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to local interconnect power rails merged with upper power rails and methods of manufacture. The structure includes: an active cell including contacts enclosed in active regions; at least one local interconnect power rail connecting to the contacts of the active regions; and at least one power rail above and connected to the at least one local interconnect power rail.
    Type: Application
    Filed: April 19, 2022
    Publication date: October 19, 2023
    Inventors: James P. MAZZA, Navneet K. JAIN, Xuelian ZHU, Jia ZENG, Mahbub RASHED
  • Publication number: 20230132912
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a logic cell layout design for high density transistors and methods of manufacture. The structure includes a plurality of active gates in a high density transistor, and at least one dummy gate which is continuous and is adjacent to at least one active gate of the active gates in a multi-row cell of the high density transistor.
    Type: Application
    Filed: November 1, 2021
    Publication date: May 4, 2023
    Inventors: James P. Mazza, Elizabeth Strehlow, Motoi Ichihashi, Xuelian Zhu, Jia Zeng
  • Publication number: 20220268805
    Abstract: Disclosed are a motion-sensitive field effect transistor (MSFET), a motion detection system, and a method. The MSFET includes a gate structure with a reservoir containing conductive fluid and gate electrode(s). Given position(s) of the gate electrode(s) and a fill level of the fluid within the reservoir, contact between the gate electrode(s) and the fluid depends upon the orientation the MSFET channel region relative to the top surface of the conductive fluid and the orientation of the MSFET channel region relative to the top surface of the conductive fluid depends upon position in space and/or movement of the MSFET and, particularly, position in space and/or movement of the chip on which the MSFET is formed. An electrical property of the MSFET in response to specific bias conditions varies depending on whether or not or to what extent the gate electrode(s) contact the fluid and is, thus, measurable for sensing chip motion.
    Type: Application
    Filed: February 24, 2021
    Publication date: August 25, 2022
    Applicant: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Romain H.A. Feuillette, David C. Pritchard, Elizabeth Strehlow, James P. Mazza
  • Patent number: 11205648
    Abstract: An integrated circuit (IC) structure with a single active region having a doping profile different than that of a set of active regions, is disclosed. The IC structure provides a single active region, e.g., a fin, on a substrate with a first doping profile, and a set of active regions, e.g., fins, electrically isolated from the single active region on the substrate. The set of active regions have a second doping profile that is different than the first doping profile of the single active region. For example, the second doping profile can have a deeper penetration into the substrate than the first doping profile.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: December 21, 2021
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Anton V. Tokranov, James P. Mazza, Elizabeth A. Strehlow, Harold Mendoza, Jay A. Mody, Clynn J. Mathew, Hong Yu, Yea-Sen Lin
  • Publication number: 20210351283
    Abstract: An integrated circuit (IC) structure with a single active region having a doping profile different than that of a set of active regions, is disclosed. The IC structure provides a single active region, e.g., a fin, on a substrate with a first doping profile, and a set of active regions, e.g., fins, electrically isolated from the single active region on the substrate. The set of active regions have a second doping profile that is different than the first doping profile of the single active region. For example, the second doping profile can have a deeper penetration into the substrate than the first doping profile.
    Type: Application
    Filed: May 5, 2020
    Publication date: November 11, 2021
    Inventors: Anton V. Tokranov, James P. Mazza, Elizabeth A. Strehlow, Harold Mendoza, Jay A. Mody, Clynn J. Mathew, Hong Yu, Yea-Sen Lin
  • Patent number: D243739
    Type: Grant
    Filed: September 4, 1975
    Date of Patent: March 22, 1977
    Inventor: James P. Mazza