Abstract: An integrated circuit including a trench capacitor has a semiconductor region in which a material composition varies in a quantity of at least one component therein such that the quantity alternates with depth a plurality of times between at least two different values. For example, a concentration of a dopant or a weight percentage of a second semiconductor material, such as germanium, in a semiconductor alloy can alternate between with depth a plurality of times between higher and lower values. The trench capacitor has an undulating capacitor dielectric layer, wherein the undulations of the capacitor dielectric layer are at least partly determined by the undulating interior surface of the trench. Such trench capacitor can provide enhanced capacitance, and can be incorporated in a memory cell such as a dynamic random access memory (“DRAM”) cell, for example.

Abstract: An integrated circuit including a trench capacitor has a semiconductor region in which a material composition varies in a quantity of at least one component therein such that the quantity alternates with depth a plurality of times between at least two different values. For example, a concentration of a dopant or a weight percentage of a second semiconductor material, such as germanium, in a semiconductor alloy can alternate between with depth a plurality of times between higher and lower values. The trench capacitor has an undulating capacitor dielectric layer, wherein the undulations of the capacitor dielectric layer are at least partly determined by the undulating interior surface of the trench. Such trench capacitor can provide enhanced capacitance, and can be incorporated in a memory cell such as a dynamic random access memory (“DRAM”) cell, for example.

Abstract: A method of fabricating a trench capacitor is provided in which a material composition of a semiconductor region of a substrate varies in a quantity of at least one component therein such that the quantity alternates with depth a plurality of times between at least two different values. For example, a concentration of a dopant or a weight percentage of a second semiconductor material in a semiconductor alloy can alternate between with depth a plurality of times between higher and lower values. In such method, the semiconductor region can be etched in a manner dependent upon the material composition to form a trench having an interior surface which undulates in a direction of depth from the major surface of the semiconductor region. Such method can further include forming a trench capacitor having an undulating capacitor dielectric layer, wherein the undulations of the capacitor dielectric layer are at least partly determined by the undulating interior surface of the trench.

Abstract: A method of fabricating a trench capacitor is provided in which a material composition of a semiconductor region of a substrate varies in a quantity of at least one component therein such that the quantity alternates with depth a plurality of times between at least two different values. For example, a concentration of a dopant or a weight percentage of a second semiconductor material in a semiconductor alloy can alternate between with depth a plurality of times between higher and lower values. In such method, the semiconductor region can be etched in a manner dependent upon the material composition to form a trench having an interior surface which undulates in a direction of depth from the major surface of the semiconductor region. Such method can further include forming a trench capacitor having an undulating capacitor dielectric layer, wherein the undulations of the capacitor dielectric layer are at least partly determined by the undulating interior surface of the trench.

Abstract: A method is provided for forming a polysilicon layer on a substrate and aligning an exposure system with an alignment feature of the substrate through the polysilicon layer. In such method, a polysilicon layer is deposited over the substrate having the alignment feature such that the polysilicon layer reaches a first temperature. The polysilicon layer is then annealed with the substrate to raise the polysilicon layer to a second temperature higher than the first temperature. A photoimageable layer is then deposited over the polysilicon layer, after which an alignment signal including light from the alignment feature is received through the annealed polysilicon layer. Using the alignment signal passing through the annealed polysilicon layer from the alignment feature, an exposure system is aligned with the substrate with improved results.

Abstract: A trench capacitor having an increased surface area. In one embodiment, the trench capacitor is a dual trench capacitor having a first trench and a second trench wherein inner walls of the trenches electrically connect. The invention also includes a single trench capacitor wherein the trench is curved around an axis substantially perpendicular to a substrate surface.

Abstract: A trench capacitor having an increased surface area. In one embodiment, the trench capacitor is a dual trench capacitor having a first trench and a second trench wherein inner walls of the trenches electrically connect. The invention also includes a single trench capacitor wherein the trench is curved around an axis substantially perpendicular to a substrate surface.

Abstract: A process of etching an oxide layer placed over a nitride layer of a substrate with high selectivity. The process comprises plasma etching the oxide layer of the substrate with a carbon and fluorine-containing gas and with a nitrogen-containing gas. A SixNy species is formed which is deposited on the nitride layer substantially in equilibrium with etching of the nitride layer.

Abstract: A trench capacitor having an increased surface area. In one embodiment, the trench capacitor is a dual trench capacitor having a first trench and a second trench wherein inner walls of the trenches electrically connect. The invention also includes a single trench capacitor wherein the trench is curved around an axis substantially perpendicular to a substrate surface.