Patents by Inventor James P. Rivers
James P. Rivers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8239580Abstract: In a Local Area Network (LAN) system, an Ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency.Type: GrantFiled: November 4, 2010Date of Patent: August 7, 2012Assignee: U.S. Ethernet Innovations, LLCInventors: Richard Hausman, Paul William Sherer, James P. Rivers, Cynthia Zikmund, Glenn W. Connery, Niles E. Strohl, Richard S. Reid
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Patent number: 7899937Abstract: In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency.Type: GrantFiled: January 21, 2000Date of Patent: March 1, 2011Assignee: U.S. Ethernet Innovations, LLCInventors: Richard Hausman, Paul William Sherer, James P. Rivers, Cynthia Zikmund, Glenn W. Connery, Niles E. Strohl, Richard S. Reid
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Publication number: 20110047302Abstract: In a Local Area Network (LAN) system, an Ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency.Type: ApplicationFiled: November 4, 2010Publication date: February 24, 2011Applicant: U.S. ETHERNET INNOVATIONSInventors: Richard Hausman, Paul William Sherer, James P. Rivers, Cynthia Zikmund, Glenn W. Connery, Niles E. Strohl, Richard S. Reid
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Patent number: 7620754Abstract: A carrier module is physically compatible with a XENPAK/X2 10 GE slot and includes a socket for accepting a non-XENPAK/X2 module and interface circuitry for providing appropriate signals to a XENPAK/X2 70-pin connector on an interior side of the carrier module. The carrier module includes a cookie, accessible by host software, identifying the type of carrier module and non-XENPAK/X2 module accepted by the carrier card.Type: GrantFiled: March 25, 2005Date of Patent: November 17, 2009Assignee: Cisco Technology, Inc.Inventors: Alan Yee, Eric Wiles, James P. Rivers, Sandeep Arvind Patel, William F. Edwards, Jr., Jeffrey Provost
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Patent number: 7590120Abstract: A method and apparatus utilized in layer 2 access switches of an Ethernet ring-based network to bridge multicast packets between a multicast VLAN and a selected VLAN coupled to a VLAN trunk port of the layer 2 access switch. The duplication of multicast streams over the ring technology is avoided while maintaining isolation between subscribers.Type: GrantFiled: November 18, 2005Date of Patent: September 15, 2009Assignee: Cisco Technology, Inc.Inventors: Pauline Shuen, James P. Rivers
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Patent number: 7539154Abstract: In a system having a plurality of nodes such as Ethernet repeaters, coupled by communication links such as cables, systems and protocols are provided for detecting and/or breaking loops. In one aspect, in response to an added link, a repeater sends a “detect loop” message containing its address to at least one neighbor. Each repeater which receives the “detect loop” message, in turn, sends it to its own neighbor, with the lesser of the received address and its own address. A repeater which receives a “detect loop” message containing its own address declares itself a master loop breaker and can isolate one of its ports to break the loop. In one aspect, a previously intentionally-isolated port can be re-activated, e.g., in response to the loss of a communication link which could potentially isolate one or more nodes.Type: GrantFiled: October 17, 2000Date of Patent: May 26, 2009Assignee: Cisco Technology, Inc.Inventors: Gordon MacKay, James P. Rivers, Rita Ousterhout, Sean X. Wang, John K. Chen
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Patent number: 7433366Abstract: A technique for allocating stack bus bandwidth based on the offered load of each stack member coupled to the stacking bus allocates access opportunities to the stack bus based on the ratio of the offered loads of the coupled stack members.Type: GrantFiled: May 16, 2003Date of Patent: October 7, 2008Assignee: Cisco Technology, Inc.Inventors: Surendra Anubolu, James P. Rivers, Stewart Findlater, David Hsi-Chen Yen
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Patent number: 7327693Abstract: A method for transmitting a message packet from a network device having multiple transmit queues at a precise time flushes all packets previously enqueued in a selected transmit queue and places the message packet in the selected queue. All other transmit queues are also flushed prior to transmitting the message packet to eliminate timing uncertainty due transmission of enqueued packets prior to the transmission of the message packet.Type: GrantFiled: March 30, 2004Date of Patent: February 5, 2008Assignee: Cisco Technology, Inc.Inventors: James P. Rivers, Pauline Shuen
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Patent number: 7277910Abstract: A ring access system, for use in system having a plurality of routing platforms coupled by redundant rings, that allows access to either ring when a token is received at a first ring if all outstanding locally-sourced data has been stripped from the second ring.Type: GrantFiled: May 20, 2003Date of Patent: October 2, 2007Assignee: Cisco Technology, Inc.Inventors: Surendra Anubolu, James P. Rivers, Stewart Findlater
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Patent number: 7274694Abstract: A cross stack port aggregation method and system associates a destination index with a received packet when it is provided to devices in the stack. Each device utilizes the destination index to access a descriptor identifying ports in the device included in the port aggregation group. An index generated from packet address data is used to select a bit in a group mask unique to each port.Type: GrantFiled: January 9, 2003Date of Patent: September 25, 2007Assignee: Cisco Technology, Inc.Inventors: Linda Cheng, Scott Emery, Stewart Findlater, James P. Rivers
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Patent number: 6587936Abstract: Data is stored in a memory in a manner which eliminates dead time which occurs when the number of words in a page which are read-out are insufficient to provide enough time for simultaneously opening the next page. If the length of a frame being stored in memory is not an exact integral multiple of words in a page, a penultimate (or earlier) page is written with fewer words than the page can hold. This allows additional words to be placed into the last page, sufficient to provide every page used for storing a frame at least a number of words equal to the number of clock cycles needed for opening a next page.Type: GrantFiled: February 21, 2001Date of Patent: July 1, 2003Assignee: Cisco Technology, Inc.Inventors: James P. Rivers, Scott A. Emery
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Patent number: 6535963Abstract: A memory system usable for a multi-casting switch or similar device includes memory which can be dynamically allocated among two or more output ports. The memory includes a plurality of severally addressable subarrays with the subarrays being dynamically associated with various output ports as the need arises. When a received frame is to be output from two or more output ports in a multi-casting fashion, the frame is written in parallel to two of the subarrays associated respectively with the output ports. Frames are written in the subarrays in the order in which they are to be read-out and providing a certain degree of inherent queuing of the stored frames, reducing or eliminating the need for pointers to achieve the desired output order.Type: GrantFiled: June 30, 1999Date of Patent: March 18, 2003Assignee: Cisco Technology, Inc.Inventor: James P. Rivers
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Patent number: 6201729Abstract: A DRAM subsystem is provided in which multiple sets of sense amps are provided, such as two or more sense amps for each DRAM column. Processes inter-leave their row and column accesses such that one process uses a first set of sense amps for accessing latched data within a page, via column access, while another process uses a second set of sense amplifiers for a row access. This permits hiding the row access behind column accesses to increase the overall bandwidth of the DRAM subsystem. In one configuration write accesses involve performing a row access after column access is complete. In one configuration, the sense amps contain a mechanism that indicates they have been written e.g., so that sense amplifier latches associated with data that was not written will take on data read from the row.Type: GrantFiled: February 1, 1999Date of Patent: March 13, 2001Assignee: Cisco Technology Inc.Inventor: James P. Rivers
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Patent number: 6112252Abstract: In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency.Type: GrantFiled: February 23, 1998Date of Patent: August 29, 2000Assignee: 3Com CorporationInventors: Richard Hausman, Paul William Sherer, James P. Rivers, Cynthia Zikmund, Glenn W. Connery, Niles E. Strohl, Richard S. Reid
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Patent number: 6078532Abstract: A memory system reducing or eliminating the effects of DRAM page-opening delays or row access delays is provided. The system uses DRAM and fast memory such as SRAM. SRAM is used to store the initial portions of data from data blocks and corresponding portions of DRAM are used to store the terminal portions of data from the data blocks. When access to a block of data is requested, DRAM row access procedures are initiated. During the delay period, while DRAM row access procedures are occurring, the initial portion of data from the requested block is read-out from SRAM. By about the time the initial data read-out from SRAM is completed, DRAM row access procedures are completed and the remaining portion of the data is read-out from DRAM.Type: GrantFiled: February 1, 1999Date of Patent: June 20, 2000Assignee: Cisco Technology Inc.Inventors: James P. Rivers, Gregory L. DeJager, David H. Yen, Stewart Findlater, Bradley Erickson, Scott A. Emery
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Patent number: 5872920Abstract: In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter may also be programmed to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency.Type: GrantFiled: July 18, 1995Date of Patent: February 16, 1999Assignee: 3Com CorporationInventors: Richard Hausman, Paul William Sherer, James P. Rivers, Cynthia Zikmund, Glenn W. Connery, Niles E. Strohl, Richard S. Reid
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Patent number: 5485584Abstract: In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency.Type: GrantFiled: January 17, 1995Date of Patent: January 16, 1996Assignee: 3Com CorporationInventors: Richard Hausman, Paul W. Sherer, James P. Rivers, Cynthia Zikmund, Glenn W. Connery, Niles E. Strohl, Richard S. Reid
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Patent number: 5420987Abstract: In a computer system having a central processing unit which employs software drivers as part of a host for controlling peripheral units and including a bus for connecting with adapters for the peripheral units, wherein each adapter has distributed intelligence means for interpreting simple command information and a nonvolatile storage element for storing default configuration information, including a default port address for communication, a method is provided for configuring such intelligent adapters connected to the bus.Type: GrantFiled: July 19, 1993Date of Patent: May 30, 1995Assignee: 3 COM CorporationInventors: Richard S. Reid, Niles Strohl, Glenn W. Connery, Paul W. Sherer, James P. Rivers
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Patent number: 5412782Abstract: In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter may also be programmed to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency.Type: GrantFiled: July 2, 1992Date of Patent: May 2, 1995Assignee: 3COM CorporationInventors: Richard Hausman, Paul W. Sherer, James P. Rivers, Cynthia Zikmund, Glenn W. Connery, Niles E. Strohl, Richard S. Reid
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Patent number: 4963702Abstract: A digitizer pad apparatus includes at least one digitizer ply where each digitizer ply has a first and a second resistor strip, each with a resistance gradient along its length, oriented in spaced apart relationship. A plurality of conductor traces are interconnected along the length of each resistor strip to extend toward and be interleaved between each other to define a sensor pad region. Each sensor pad region defines a dimensional direction. A shunt ply is positioned to face the sensor pad region in normally non-conducting relationship so that when a selected area is pressed into contact with the conductor traces, conduction between adjacent conductor traces via the shunt ply will occur in the selected contact area. The selected contact area has a first edge and a second edge opposite the first edge along the defined dimensional direction.Type: GrantFiled: February 9, 1989Date of Patent: October 16, 1990Assignee: Interlink Electronics, Inc.Inventors: Stuart I. Yaniger, James P. Rivers