Patents by Inventor James P. Shiely
James P. Shiely has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11200362Abstract: Systems and techniques for three-dimension (3D) resist profile aware resolution enhancement techniques are described. 3D resist profile aware resolution enhancement models can be calibrated based on empirical data. Next, the 3D resist profile aware resolution enhancement models can be used in one or more applications, including, but not limited to, lithography verification, etch correction, optical proximity correction, and assist feature placement.Type: GrantFiled: April 14, 2017Date of Patent: December 14, 2021Assignee: Synopsys, Inc.Inventors: Hua Song, Cheng En Wu, James P. Shiely
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Publication number: 20170220723Abstract: Systems and techniques for three-dimension (3D) resist profile aware resolution enhancement techniques are described. 3D resist profile aware resolution enhancement models can be calibrated based on empirical data. Next, the 3D resist profile aware resolution enhancement models can be used in one or more applications, including, but not limited to, lithography verification, etch correction, optical proximity correction, and assist feature placement.Type: ApplicationFiled: April 14, 2017Publication date: August 3, 2017Applicant: Synopsys, Inc.Inventors: Hua Song, Cheng En Wu, James P. Shiely
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Patent number: 9646127Abstract: Systems and techniques for using a three-dimension (3D) resist profile aware etch-bias model are described. A 3D resist profile aware etch-bias model can be calibrated based on empirical data. Next, the 3D resist profile aware etch-bias model can be used in one or more applications, including, but not limited to, lithography verification, etch correction, optical proximity correction, and assist feature placement.Type: GrantFiled: May 14, 2015Date of Patent: May 9, 2017Assignee: SYNOPSYS, INC.Inventors: Hua Song, Cheng En Wu, James P. Shiely
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Publication number: 20160335384Abstract: Systems and techniques for using a three-dimension (3D) resist profile aware etch-bias model are described. A 3D resist profile aware etch-bias model can be calibrated based on empirical data. Next, the 3D resist profile aware etch-bias model can be used in one or more applications, including, but not limited to, lithography verification, etch correction, optical proximity correction, and assist feature placement.Type: ApplicationFiled: May 14, 2015Publication date: November 17, 2016Applicant: SYNOPSYS, INC.Inventors: Hua Song, Cheng En Wu, James P. Shiely
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Patent number: 9484186Abstract: Processes and apparatuses are described for modeling and correcting electron-beam (e-beam) proximity effects during e-beam lithography. An uncalibrated e-beam model, which includes a long-range component and a short-range component, can be calibrated based on one or more test layouts. During correction, a first resist intensity map can be computed based on the long-range component of the calibrated e-beam model and a mask layout. Next, a target pattern in the mask layout can be corrected by, iteratively: (1) computing a second resist intensity map based on the short-range component of the calibrated e-beam model and the target pattern; (2) obtaining a combined resist intensity map by combining the first resist intensity map and the second resist intensity map; and (3) adjusting the target pattern based on the combined resist intensity map and the design intent.Type: GrantFiled: October 23, 2012Date of Patent: November 1, 2016Assignee: SYNOPSYS, INC.Inventors: Hua Song, Irene Y. Su, James P. Shiely
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Patent number: 8972229Abstract: Computer-readable medium and methods for photolithographic simulation of scattering. A design layout comprising a layout polygon is received. A skeleton representation of a mask shape that is created responsive to e-beam writing of the layout polygon is generated. The skeleton representation is defined by a plurality of skeleton points. Individual scattering patterns for the skeleton points are selected from a lookup table of pre-determined scattering patterns. Each of the individual scattering patterns representing an amount of optical scattering for a corresponding one of the skeleton points. A simulated wafer image is produced responsive to the individual scattering patterns.Type: GrantFiled: March 14, 2013Date of Patent: March 3, 2015Assignee: Synopsys, Inc.Inventors: Zhijie Deng, Qiliang Yan, James P. Shiely
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Publication number: 20140114634Abstract: Processes and apparatuses are described for modeling and correcting electron-beam (e-beam) proximity effects during e-beam lithography. An uncalibrated e-beam model, which includes a long-range component and a short-range component, can be calibrated based on one or more test layouts. During correction, a first resist intensity map can be computed based on the long-range component of the calibrated e-beam model and a mask layout. Next, a target pattern in the mask layout can be corrected by, iteratively: (1) computing a second resist intensity map based on the short-range component of the calibrated e-beam model and the target pattern; (2) obtaining a combined resist intensity map by combining the first resist intensity map and the second resist intensity map; and (3) adjusting the target pattern based on the combined resist intensity map and the design intent.Type: ApplicationFiled: October 23, 2012Publication date: April 24, 2014Applicant: SYNOPSYS, INC.Inventors: Hua Song, Irene Y. Su, James P. Shiely
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Publication number: 20140032199Abstract: Computer-readable medium and methods for photolithographic simulation of scattering. A design layout comprising a layout polygon is received. A skeleton representation of a mask shape that is created responsive to e-beam writing of the layout polygon is generated. The skeleton representation is defined by a plurality of skeleton points. Individual scattering patterns for the skeleton points are selected from a lookup table of pre-determined scattering patterns. Each of the individual scattering patterns representing an amount of optical scattering for a corresponding one of the skeleton points. A simulated wafer image is produced responsive to the individual scattering patterns.Type: ApplicationFiled: March 14, 2013Publication date: January 30, 2014Applicant: SYNOPSYS, INC.Inventors: Zhijie Deng, Qiliang Yan, James P. Shiely
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Patent number: 8601404Abstract: Systems and techniques for modeling the EUV lithography shadowing effect are described. Some embodiments described herein provide a process model that includes an EUV lithography shadowing effect component. Polygon edges in a layout can be dissected into a set of segments. Next, the EUV lithography shadowing effect component can be used to bias each segment. The modified layout having the biased segments can then be used as input for other components in the process model.Type: GrantFiled: January 31, 2012Date of Patent: December 3, 2013Assignee: Synopsys, Inc.Inventors: Hua Song, James P. Shiely, Lena Zavyalova
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Patent number: 8423917Abstract: One embodiment of the present invention provides a system that determines image intensity at a location in a photoresist (PR) layer on a wafer. During operation, the system receives a set of masks which were used to generate one or more patterned layers of a multilayer structure on the wafer, wherein a patterned layer includes a set of reflectors on a top surface of the patterned layer, which correspond to patterns in a patterned-layer mask in the set of masks, wherein a reflector reflects light from a light source during a photolithography process. The system then generates a first virtual mask based on the first mask and the patterned-layer mask, wherein the first virtual mask uses a clear area to model a reflector in the set of reflectors. Next, the system determines the image intensity value at the location on the PR layer based at least on the first mask and the first virtual mask.Type: GrantFiled: July 30, 2009Date of Patent: April 16, 2013Assignee: Synopsys, Inc.Inventors: Hua Song, James P. Shiely, Qiaolin Zhang
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Publication number: 20120240086Abstract: Systems and techniques for modeling the EUV lithography shadowing effect are described. Some embodiments described herein provide a process model that includes an EUV lithography shadowing effect component. Polygon edges in a layout can be dissected into a set of segments. Next, the EUV lithography shadowing effect component can be used to bias each segment. The modified layout having the biased segments can then be used as input for other components in the process model.Type: ApplicationFiled: January 31, 2012Publication date: September 20, 2012Applicant: SYNOPSYS, INC.Inventors: Hua Song, James P. Shiely, Lena Zavyalova
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Patent number: 8132128Abstract: One embodiment of the present invention provides a system that performs lithography verification for a double-patterning process on a mask layout without performing a full contour simulation of the mask layout. During operation, the system starts by receiving a first mask which is used in a first lithography step of the double-patterning process, and a second mask which is used in a second lithography step of the double-patterning process. Note that the first mask and the second mask are obtained by partitioning the mask layout. Next, the system receives an evaluation point on the mask layout. The system then determines whether the evaluation point is exclusively located on a polygon of the first mask, exclusively located on a polygon of the second mask, or located elsewhere. The system next computes a printing indicator at the evaluation point for the mask layout based on whether the evaluation point is exclusively located on a polygon of the first mask or exclusively located on a polygon of the second mask.Type: GrantFiled: October 31, 2008Date of Patent: March 6, 2012Assignee: Synopsys, Inc.Inventors: Hua Song, Lantian Wang, Gerard Terrence Luk-Pat, James P. Shiely
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Patent number: 7933471Abstract: One embodiment of the present invention provides a system that reduces computational complexity in simulating an image resulting from an original mask and an optical transmission system. During operation, the system obtains a set transmission cross coefficient (TCC) kernel functions based on the optical transmission system, and obtains a set of transmission functions for a representative pattern which contains features representative of the original mask. The system constructs a new set of kernel functions based on the TCC kernel functions and the transmission functions for the representative pattern, wherein responses to the new kernel functions in a resulting image corresponding to the representative pattern are substantially uncorrelated with one another. The system further produces an intensity distribution of a resulting image corresponding to the original mask based on the new kernel functions, thereby facilitating prediction of a layout that can be produced from the original mask.Type: GrantFiled: March 9, 2007Date of Patent: April 26, 2011Assignee: Synopsys, Inc.Inventors: Jianliang Li, Qiliang Yan, Lawrence S. Melvin, III, James P. Shiely
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Publication number: 20110029940Abstract: One embodiment of the present invention provides a system that determines image intensity at a location in a photoresist (PR) layer on a wafer. During operation, the system receives a set of masks which were used to generate one or more patterned layers of a multilayer structure on the wafer, wherein a patterned layer includes a set of reflectors on a top surface of the patterned layer, which correspond to patterns in a patterned-layer mask in the set of masks, wherein a reflector reflects light from a light source during a photolithography process. The system then generates a first virtual mask based on the first mask and the patterned-layer mask, wherein the first virtual mask uses a clear area to model a reflector in the set of reflectors. Next, the system determines the image intensity value at the location on the PR layer based at least on the first mask and the first virtual mask.Type: ApplicationFiled: July 30, 2009Publication date: February 3, 2011Applicant: SYNOPSYS, INC.Inventors: Hua Song, James P. Shiely, Qiaolin Zhang
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Patent number: 7784018Abstract: One embodiment of the present invention provides a system that identifies an area in a mask layout which is likely to cause manufacturing problems. During operation, the system creates an on-target process model that models a semiconductor manufacturing process under nominal (e.g., optimal) process conditions. The system also creates one or more off-target process models that model the semiconductor manufacturing process under one or more arbitrary (e.g., non-optimal) process conditions. Next, the system computes a process-sensitivity model using the on-target process model and the off-target process models. The system then computes a gradient-magnitude of the process-sensitivity model. Next, the system identifies a problem area in the mask layout using the gradient-magnitude of the process-sensitivity model. Note that identifying the problem area allows it to be corrected, which improves the manufacturability of the mask layout.Type: GrantFiled: May 8, 2007Date of Patent: August 24, 2010Assignee: Synopsys, Inc.Inventors: Lawrence S. Melvin, III, James P. Shiely, Qiliang Yan
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Publication number: 20100115489Abstract: One embodiment of the present invention provides a system that performs lithography verification for a double-patterning process on a mask layout without performing a full contour simulation of the mask layout. During operation, the system starts by receiving a first mask which is used in a first lithography step of the double-patterning process, and a second mask which is used in a second lithography step of the double-patterning process. Note that the first mask and the second mask are obtained by partitioning the mask layout. Next, the system receives an evaluation point on the mask layout. The system then determines whether the evaluation point is exclusively located on a polygon of the first mask, exclusively located on a polygon of the second mask, or located elsewhere. The system next computes a printing indicator at the evaluation point for the mask layout based on whether the evaluation point is exclusively located on a polygon of the first mask or exclusively located on a polygon of the second mask.Type: ApplicationFiled: October 31, 2008Publication date: May 6, 2010Applicant: SYNOPSYS, INC.Inventors: Hua Song, Lantian Wang, Gerard Terrence Luk-Pat, James P. Shiely
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Patent number: 7494751Abstract: One embodiment of the present invention provides a system that improves the depth of focus during an optical lithography process. During operation, the system receives a mask layout. The system then selects an edge in the mask layout. Next, the system adds a notch to the edge to improve the depth of focus by helping to maintain a critical dimension associated with the edge as the optical lithography process drifts out of focus. Note that adding a notch to the edge adds a high spatial-frequency component to the mask layout. This high spatial-frequency component degrades as the optical lithography process drifts out of focus. This degradation causes the mask layout to allow more light into the pattern, which helps maintain the critical dimension, thereby improving depth of focus.Type: GrantFiled: January 27, 2005Date of Patent: February 24, 2009Assignee: Synopsys, Inc.Inventors: Lawrence S. Melvin, III, James P. Shiely
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Publication number: 20080219590Abstract: One embodiment of the present invention provides a system that reduces computational complexity in simulating an image resulting from an original mask and an optical transmission system. During operation, the system obtains a set transmission cross coefficient (TCC) kernel functions based on the optical transmission system, and obtains a set of transmission functions for a representative pattern which contains features representative of the original mask. The system constructs a new set of kernel functions based on the TCC kernel functions and the transmission functions for the representative pattern, wherein responses to the new kernel functions in a resulting image corresponding to the representative pattern are substantially uncorrelated with one another. The system further produces an intensity distribution of a resulting image corresponding to the original mask based on the new kernel functions, thereby facilitating prediction of a layout that can be produced from the original mask.Type: ApplicationFiled: March 9, 2007Publication date: September 11, 2008Inventors: Jianliang Li, Qiliang Yan, Lawrence S. Melvin, James P. Shiely
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Patent number: 7320119Abstract: One embodiment of the present invention provides a system that identifies a problem edge in a mask layout which is likely to have manufacturing problems. During operation, the system creates an on-target process model that models a semiconductor manufacturing process under nominal process conditions. The system also creates one or more off-target process models that model the semiconductor manufacturing process under one or more process conditions that are different from nominal process conditions. Next, the system computes a process-sensitivity model using the on-target process model and the off-target process models. The system then computes an edge-detecting process-sensitivity model by convolving the process-sensitivity model with an edge-detecting function which can be used to detect edges in an image. Next, the system identifies a problem edge in the mask layout using the edge-detecting process-sensitivity model.Type: GrantFiled: May 6, 2005Date of Patent: January 15, 2008Assignee: Synopsys, Inc.Inventors: Lawrence S. Melvin, III, James P. Shiely, Qiliang Yan, Benjamin D. Painter
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Patent number: 7308673Abstract: One embodiment of the present invention provides a system that improves lithography performance by correcting for 3D mask effects. During operation the system receives a mask layout that contains etched regions, called shifters, which can have a phase shift relative to other regions. Next, the system chooses a shifter in the mask layout. The system then corrects for 3D mask effects by, iteratively, (a) selecting a region within the shifter, (b) adjusting the phase shift of the selected region in a simulation model to account for 3D mask effects, and (c) modifying the shape of the shifter based on the difference between a desired pattern and a simulated pattern generated using the simulation model.Type: GrantFiled: January 10, 2005Date of Patent: December 11, 2007Assignee: Synopsys, Inc.Inventors: Lawrence S. Melvin, III, Qiliang Yan, James P. Shiely