Abstract: A system includes a partitionable multi-processor motherboard that has multiple central processing units, wherein the multi-processor motherboard may be configured to operate as a single unified node or configured to operate as multiple independent partitioned nodes. The system further comprises a single power button that is accessible to a user, wherein the single power button generates an output signal while being pressed, and an integrated circuit installed on the motherboard and connected to receive the output signal from the power button, wherein the integrated circuit stores a first button press gesture definition associated with selection of a first partitioned node, a second button press gesture definition associated with selection of a second partitioned node, and a third button press gesture definition associated with sequencing power to the selected one of the first or second partitioned nodes.

Abstract: A computer program product includes a non-volatile computer readable medium and non-transitory program instructions embodied therein, the program instructions being configured to be executable by a processor of a baseboard management controller in a multi-processor system to cause the processor to perform various operations. The operations include initiating disabling of a processor interconnect between first and second central processing units in the multi-processor system and initiating boot of the first central processing unit, wherein the first central processing unit operates in a first partitioned node independent of the second central processing unit.

Abstract: Embodiments provide a method and computer program product including program instructions executable by a baseboard management controller in a multi-processor system to perform various operations. The operations include detecting a number of memory modules connected to each of a plurality of central processing units (CPUs) in the multi-processor system during boot, initiating operation of the multi-processor system as a single unified node in response to each of the CPUs being connected to an equal number of memory modules, and initiating partitioning of the multi-processor system into a first partitioned node and a second partitioned node in response to a first set of one or more of the CPUs each being connected to a first number of memory modules and a second set of one or more of the CPUs each being connected to a second number of memory modules that is different than the first number of memory modules.

Abstract: A bi-directional voltage translator is disclosed. The bi-directional voltage translator includes a step-up voltage translator for converting signals of a first voltage level to signals of a second voltage level, and a step-down voltage translator for converting signals of the second voltage level to signals of the first voltage level. The step-up voltage translator includes a first source sense circuit, a first block feedback circuit and a first output driver circuit. The step-down voltage translator includes a second source sense circuit, a second block feedback circuit and a second output driver circuit.

Abstract: In a communication system having a plurality of networks, a method of achieving network separation between first and second networks is described. First and second networks with respective first and second degrees of trust are defined, the first degree of trust being higher than the second degree of trust. Communication between the first and second networks is enabled via a network interface system having a protocol stack, the protocol stack implemented by the network interface system in an application layer. Data communication from the second network to the first network is enabled while data communication from the first network to the second network is minimized.