Patents by Inventor James Patrick Koonmen
James Patrick Koonmen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210357570Abstract: A defect prediction method for a device manufacturing process involving processing a portion of a design layout onto a substrate, the method including: identifying a hot spot from the portion of the design layout; determining a range of values of a processing parameter of the device manufacturing process for the hot spot, wherein when the processing parameter has a value outside the range, a defect is produced from the hot spot with the device manufacturing process; determining an actual value of the processing parameter; determining or predicting, using the actual value, existence, probability of existence, a characteristic, or a combination thereof, of a defect produced from the hot spot with the device manufacturing process.Type: ApplicationFiled: July 30, 2021Publication date: November 18, 2021Applicant: ASML NETHERLANDS B.V.Inventors: Christophe David FOUQUET, Bernardo KASTRUP, Arie Jeffrey DEN BOEF, Johannes Catharinus Hubertus MULKENS, James Benedict KAVANAGH, James Patrick KOONMEN, Neal Patrick CALLAN
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Patent number: 11080459Abstract: A defect prediction method for a device manufacturing process involving processing a portion of a design layout onto a substrate, the method including: identifying a hot spot from the portion of the design layout; determining a range of values of a processing parameter of the device manufacturing process for the hot spot, wherein when the processing parameter has a value outside the range, a defect is produced from the hot spot with the device manufacturing process; determining an actual value of the processing parameter; determining or predicting, using the actual value, existence, probability of existence, a characteristic, or a combination thereof, of a defect produced from the hot spot with the device manufacturing process.Type: GrantFiled: February 28, 2020Date of Patent: August 3, 2021Assignee: ASML Netherlands B.V.Inventors: Christophe David Fouquet, Bernardo Kastrup, Arie Jeffrey Den Boef, Johannes Catharinus Hubertus Mulkens, James Benedict Kavanagh, James Patrick Koonmen, Neal Patrick Callan
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Publication number: 20200218849Abstract: A defect prediction method for a device manufacturing process involving processing a portion of a design layout onto a substrate, the method including: identifying a hot spot from the portion of the design layout; determining a range of values of a processing parameter of the device manufacturing process for the hot spot, wherein when the processing parameter has a value outside the range, a defect is produced from the hot spot with the device manufacturing process; determining an actual value of the processing parameter; determining or predicting, using the actual value, existence, probability of existence, a characteristic, or a combination thereof, of a defect produced from the hot spot with the device manufacturing process.Type: ApplicationFiled: February 28, 2020Publication date: July 9, 2020Applicant: ASML NETHERLANDS B.V.Inventors: Christophe David Fouquet, Bernardo Kastrup, Arie Jeffrey Den Boef, Johannes Catharinus Hubertus Mulkens, James Benedict Kavanagh, James Patrick Koonmen, Neal Patrick Callan
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Publication number: 20200189192Abstract: Systems and methods for tuning photolithographic processes are described. A model of a target scanner is maintained defining sensitivity of the target scanner with reference to a set of tunable parameters. A differential model represents deviations of the target scanner from the reference. The target scanner may be tuned based on the settings of the reference scanner and the differential model. Performance of a family of related scanners may be characterized relative to the performance of a reference scanner. Differential models may include information such as parametric offsets and other differences that may be used to simulate the difference in imaging behavior.Type: ApplicationFiled: February 21, 2020Publication date: June 18, 2020Applicant: ASML NETHERLANDS B.V.Inventors: Yu CAO, Wenjin SHAO, Ronaldus Johannes Gijsbertus GOOSSENS, Jun YE, James Patrick KOONMEN
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Patent number: 10579772Abstract: A computer-implemented defect prediction method for a device manufacturing process involving processing a portion of a design layout onto a substrate, the method including: identifying a hot spot from the portion of the design layout; determining a range of values of a processing parameter of the device manufacturing process for the hot spot, wherein when the processing parameter has a value outside the range, a defect is produced from the hot spot with the device manufacturing process; determining an actual value of the processing parameter; determining or predicting, using the actual value, existence, probability of existence, a characteristic, or a combination thereof, of a defect produced from the hot spot with the device manufacturing process.Type: GrantFiled: June 4, 2018Date of Patent: March 3, 2020Assignee: ASML Netherlands B.V.Inventors: Christophe David Fouquet, Bernardo Kastrup, Arie Jeffrey Den Boef, Johannes Catharinus Hubertus Mulkens, James Benedict Kavanagh, James Patrick Koonmen, Neal Patrick Callan
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Patent number: 10569469Abstract: Systems and methods for tuning photolithographic processes are described. A model of a target scanner is maintained defining sensitivity of the target scanner with reference to a set of tunable parameters. A differential model represents deviations of the target scanner from the reference. The target scanner may be tuned based on the settings of the reference scanner and the differential model. Performance of a family of related scanners may be characterized relative to the performance of a reference scanner. Differential models may include information such as parametric offsets and other differences that may be used to simulate the difference in imaging behavior.Type: GrantFiled: October 28, 2014Date of Patent: February 25, 2020Assignee: ASML Netherlands B.V.Inventors: Yu Cao, Wenjin Shao, Ronaldus Johannes Gijsbertus Goossens, Jun Ye, James Patrick Koonmen
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Publication number: 20180365369Abstract: A computer-implemented defect prediction method for a device manufacturing process involving processing a portion of a design layout onto a substrate, the method including: identifying a hot spot from the portion of the design layout; determining a range of values of a processing parameter of the device manufacturing process for the hot spot, wherein when the processing parameter has a value outside the range, a defect is produced from the hot spot with the device manufacturing process; determining an actual value of the processing parameter; determining or predicting, using the actual value, existence, probability of existence, a characteristic, or a combination thereof, of a defect produced from the hot spot with the device manufacturing process.Type: ApplicationFiled: June 4, 2018Publication date: December 20, 2018Applicant: ASML NETHERLANDS B.V.Inventors: Christophe David FOUQUET, Bernardo KASTRUP, Arie Jeffrey Den Boef, Johannes Catharinus Hubertus Mulkens, James Benedict Kavanagh, James Patrick Koonmen, Neal Patrick Callan
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Patent number: 10137643Abstract: Systems and methods for process simulation are described. The methods may use a reference model identifying sensitivity of a reference scanner to a set of tunable parameters. Chip fabrication from a chip design may be simulated using the reference model, wherein the chip design is expressed as one or more masks. An iterative retuning and simulation process may be used to optimize critical dimension in the simulated chip and to obtain convergence of the simulated chip with an expected chip. Additionally, a designer may be provided with a set of results from which an updated chip design is created.Type: GrantFiled: August 11, 2014Date of Patent: November 27, 2018Assignee: ASML NETHERLANDS B.V.Inventors: Yu Cao, Wenjin Shao, Ronaldus Johannes Gijsbertus Goossens, Jun Ye, James Patrick Koonmen
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Patent number: 10007192Abstract: The present invention provides a number of innovations in the area of computational process control (CPC). CPC offers unique diagnostic capability during chip manufacturing cycle by analyzing temporal drift of a lithography apparatus/ process, and provides a solution towards achieving performance stability of the lithography apparatus/process. Embodiments of the present invention enable optimized process windows and higher yields by keeping performance of a lithography apparatus and/or parameters of a lithography process substantially close to a pre-defined baseline condition. This is done by comparing the measured temporal drift to a baseline performance using a lithography process simulation model. Once in manufacturing, CPC optimizes a scanner for specific patterns or reticles by leveraging wafer metrology techniques and feedback loop, and monitors and controls, among other things, overlay and/or CD uniformity (CDU) performance over time to continuously maintain the system close to the baseline condition.Type: GrantFiled: October 6, 2014Date of Patent: June 26, 2018Assignee: ASML NETHERLANDS B.V.Inventors: Jun Ye, Yu Cao, James Patrick Koonmen
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Patent number: 9990462Abstract: Disclosed herein is a computer-implemented defect prediction method for a device manufacturing process involving processing a portion of a design layout onto a substrate, the method comprising: identifying a hot spot from the portion of the design layout; determining a range of values of a processing parameter of the device manufacturing process for the hot spot, wherein when the processing parameter has a value outside the range, a defect is produced from the hot spot with the device manufacturing process; determining an actual value of the processing parameter; determining or predicting, using the actual value, existence, probability of existence, a characteristic, or a combination thereof, of a defect produced from the hot spot with the device manufacturing process.Type: GrantFiled: October 31, 2016Date of Patent: June 5, 2018Assignee: ASML NETHERLANDS B.V.Inventors: Christophe David Fouquet, Bernardo Kastrup, Arie Jeffrey Den Boef, Johannes Catharinus Hubertus Mulkens, James Benedict Kavanagh, James Patrick Koonmen, Neal Patrick Callan
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Patent number: 9645509Abstract: The present invention relates to a method for simulating aspects of a lithographic process. According to certain aspects, the present invention uses transmission cross coefficients to represent the scanner data and models. According to other aspects, the present invention enables sensitive data regarding various scanner subsystems to be hidden from third party view, while providing data and models useful for accurate lithographic simulation.Type: GrantFiled: October 29, 2009Date of Patent: May 9, 2017Assignee: ASML NETHERLANDS B.V.Inventors: Yu Cao, Jun Ye, James Patrick Koonmen, Stefan Hunsche
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Publication number: 20170046473Abstract: Disclosed herein is a computer-implemented defect prediction method for a device manufacturing process involving processing a portion of a design layout onto a substrate, the method comprising: identifying a hot spot from the portion of the design layout; determining a range of values of a processing parameter of the device manufacturing process for the hot spot, wherein when the processing parameter has a value outside the range, a defect is produced from the hot spot with the device manufacturing process; determining an actual value of the processing parameter; determining or predicting, using the actual value, existence, probability of existence, a characteristic, or a combination thereof, of a defect produced from the hot spot with the device manufacturing process.Type: ApplicationFiled: October 31, 2016Publication date: February 16, 2017Applicant: ASML NETHERLANDS B.V.Inventors: Christophe David FOUQUET, Bernardo KASTRUP, Arie Jeffrey DEN BOEF, Johannes Catharinus Hubertus MULKENS, James Benedict KAVANAGH, James Patrick KOONMEN, Neal Patrick CALLAN
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Patent number: 9507907Abstract: Disclosed herein is a computer-implemented defect prediction method for a device manufacturing process involving processing a portion of a design layout onto a substrate, the method comprising: identifying a hot spot from the portion of the design layout; determining a range of values of a processing parameter of the device manufacturing process for the hot spot, wherein when the processing parameter has a value outside the range, a defect is produced from the hot spot with the device manufacturing process; determining an actual value of the processing parameter; and determining or predicting, using the actual value, an existence, a probability of existence, a characteristic, or a combination selected therefrom, of a defect produced from the hot spot with the device manufacturing process.Type: GrantFiled: June 4, 2015Date of Patent: November 29, 2016Assignee: ASML NETHERLANDS B.V.Inventors: Christophe David Fouquet, Bernardo Kastrup, Arie Jeffrey Den Boef, Johannes Catharinus Hubertus Mulkens, James Benedict Kavanagh, James Patrick Koonmen, Neal Patrick Callan
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Publication number: 20150356233Abstract: Disclosed herein is a computer-implemented defect prediction method for a device manufacturing process involving processing a portion of a design layout onto a substrate, the method comprising: identifying a hot spot from the portion of the design layout; determining a range of values of a processing parameter of the device manufacturing process for the hot spot, wherein when the processing parameter has a value outside the range, a defect is produced from the hot spot with the device manufacturing process; determining an actual value of the processing parameter; determining or predicting, using the actual value, existence, probability of existence, a characteristic, or a combination thereof, of a defect produced from the hot spot with the device manufacturing process.Type: ApplicationFiled: June 4, 2015Publication date: December 10, 2015Applicant: ASML NETHERLANDS B.V.Inventors: Christophe David FOUQUET, Bernardo KASTRUP, Arie Jeffrey DEN BOEF, Johannes Catharinus Hubertus MULKENS, James Benedict KAVANAGH, James Patrick KOONMEN, Neal Patrick CALLAN
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Publication number: 20150045935Abstract: Systems and methods for tuning photolithographic processes are described. A model of a target scanner is maintained defining sensitivity of the target scanner with reference to a set of tunable parameters. A differential model represents deviations of the target scanner from the reference. The target scanner may be tuned based on the settings of the reference scanner and the differential model. Performance of a family of related scanners may be characterized relative to the performance of a reference scanner. Differential models may include information such as parametric offsets and other differences that may be used to simulate the difference in imaging behavior.Type: ApplicationFiled: October 28, 2014Publication date: February 12, 2015Applicant: ASML NETHERLANDS B.V.Inventors: Yu CAO, Wenjin SHAO, Ronaldus Johannes Gijsbertus GOOSSENS, Jun YE, James Patrick KOONMEN
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Publication number: 20150025668Abstract: The present invention provides a number of innovations in the area of computational process control (CPC). CPC offers unique diagnostic capability during chip manufacturing cycle by analyzing temporal drift of a lithography apparatus/ process, and provides a solution towards achieving performance stability of the lithography apparatus/process. Embodiments of the present invention enable optimized process windows and higher yields by keeping performance of a lithography apparatus and/or parameters of a lithography process substantially close to a pre-defined baseline condition. This is done by comparing the measured temporal drift to a baseline performance using a lithography process simulation model. Once in manufacturing, CPC optimizes a scanner for specific patterns or reticles by leveraging wafer metrology techniques and feedback loop, and monitors and controls, among other things, overlay and/or CD uniformity (CDU) performance over time to continuously maintain the system close to the baseline condition.Type: ApplicationFiled: October 6, 2014Publication date: January 22, 2015Applicant: ASML NETHERLANDS B.V.Inventors: Jun YE, Yu CAO, James Patrick KOONMEN
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Publication number: 20140351773Abstract: Systems and methods for process simulation are described. The methods may use a reference model identifying sensitivity of a reference scanner to a set of tunable parameters. Chip fabrication from a chip design may be simulated using the reference model, wherein the chip design is expressed as one or more masks. An iterative retuning and simulation process may be used to optimize critical dimension in the simulated chip and to obtain convergence of the simulated chip with an expected chip. Additionally, a designer may be provided with a set of results from which an updated chip design is created.Type: ApplicationFiled: August 11, 2014Publication date: November 27, 2014Applicant: ASML NETHERLANDS B.V.Inventors: Yu CAO, Wenjin SHAO, Ronaldus Johannes Gijsbertus GOOSSENS, Jun YE, James Patrick KOONMEN
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Patent number: 8874423Abstract: Systems and methods for tuning photolithographic processes are described. A model of a target scanner is maintained defining sensitivity of the target scanner with reference to a set of tunable parameters. A differential model represents deviations of the target scanner from the reference. The target scanner may be tuned based on the settings of the reference scanner and the differential model. Performance of a family of related scanners may be characterized relative to the performance of a reference scanner. Differential models may include information such as parametric offsets and other differences that may be used to simulate the difference in imaging behavior.Type: GrantFiled: October 28, 2013Date of Patent: October 28, 2014Assignee: ASML Netherlands B.V.Inventors: Yu Cao, Wenjin Shao, Ronaldus Johannes Gijsbertus Goossens, Jun Ye, James Patrick Koonmen
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Patent number: 8856694Abstract: The present invention provides a number of innovations in the area of computational process control (CPC). CPC offers unique diagnostic capability during chip manufacturing cycle by analyzing temporal drift of a lithography apparatus/ process, and provides a solution towards achieving performance stability of the lithography apparatus/process. Embodiments of the present invention enable optimized process windows and higher yields by keeping performance of a lithography apparatus and/or parameters of a lithography process substantially close to a pre-defined baseline condition. This is done by comparing the measured temporal drift to a baseline performance using a lithography process simulation model. Once in manufacturing, CPC optimizes a scanner for specific patterns or reticles by leveraging wafer metrology techniques and feedback loop, and monitors and controls, among other things, overlay and/or CD uniformity (CDU) performance over time to continuously maintain the system close to the baseline condition.Type: GrantFiled: May 25, 2012Date of Patent: October 7, 2014Assignee: ASML Netherlands B.V.Inventors: Jun Ye, Yu Cao, James Patrick Koonmen
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Patent number: 8806387Abstract: Systems and methods for process simulation are described. The methods may use a reference model identifying sensitivity of a reference scanner to a set of tunable parameters. Chip fabrication from a chip design may be simulated using the reference model, wherein the chip design is expressed as one or more masks. An iterative retuning and simulation process may be used to optimize critical dimension in the simulated chip and to obtain convergence of the simulated chip with an expected chip. Additionally, a designer may be provided with a set of results from which an updated chip design is created.Type: GrantFiled: May 29, 2009Date of Patent: August 12, 2014Assignee: ASML Netherlands B.V.Inventors: Yu Cao, Wenjin Shao, Ronaldus Johannes Gijsbertus Goossens, Jun Ye, James Patrick Koonmen