Abstract: The present disclosure describes a semiconductor IC device that includes a locally displaced to transistor active area. The locally displaced top active region may be associated with a top transistor that is stacked over the bottom transistor. The locally displaced top active region is offset or shifted with respect to the bottom active region and includes a displaced portion or region thereof that is offset or shifted to a lesser extent. For example, the top transistor active area may include a first portion that is laterally offset relative to the bottom active region by a first dimension and a locally displaced portion that is laterally offset relative to the bottom active region by a second dimension that is less than the first dimension. The displaced portion may allow adequate space for placement of a through interconnect without otherwise increasing an associated transistor horizontal cell dimension.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first stack of transistors in a first transistor cell, the first stack of transistors including a first top transistor and a first bottom transistor; a second stack of transistors in a second transistor cell, the second stack of transistors including a second top transistor and a second bottom transistor, the second transistor cell being adjacent to the first transistor cell; and at least one power plane between the first top transistor and the first bottom transistor and between the second top transistor and the second bottom transistor. A method of forming the same is also provided.

Abstract: A semiconductor device includes a first region including forksheet devices having a first cell height and a second region including nanosheet devices having a second cell height. The forksheet devices and the nanosheet devices share active region rows, and the second cell height is larger than the first cell height.

Abstract: A semiconductor device includes a lower device layer having a bottom transistor and an upper device layer having a transistor, positioned above and laterally offset from the bottom transistor. A backside power plane is below the lower device layer. A backside bottom gate contact penetrates through the backside power plane to contact a gate of the bottom transistor. A dielectric liner is between the backside power plane and the backside bottom gate contact.

Abstract: Three dimensional electronic structures are provided in which ferromagnetic elements are present in both a first substrate and a second substrate to provide self-aligned contact of metal wiring that is present in the first substrate and the second substrate.

Abstract: A semiconductor device includes a first field and a second field connected to the first field across a stitch region by a metal line. A merged portion within the stitch region connects portions of the metal line between the first field and the second field. The portions of the metal line each include angled portions that extend beyond a width of the metal line.

Abstract: A semiconductor device is provided which includes a pair of fork sheet transistors. Each fork sheet transistor includes a plurality of vertically stacked, spaced apart semiconductor material nanosheets and a gate all around (GAA) structure formed on the semiconductor material nanosheets. The semiconductor device also includes a dielectric pillar, composed of a first dielectric material and located between the pair of fork sheet transistors. The semiconductor device further includes: first inner spacer portions, composed of a second dielectric material, located between the dielectric pillar and inner edges of the semiconductor material nanosheets of each fork sheet transistor; and second inner spacer portions, composed of the second dielectric material, and located between each of the semiconductor material nanosheets, above the semiconductor material nanosheets and below the semiconductor material nanosheets.

Abstract: A semiconductor device includes a stacked transistor structure having field effect transistors on two levels. Active regions are longitudinally disposed on each of the two levels. The active regions include source/drain regions and channel regions. An active region of the active regions includes a transition region wherein longitudinal portions of the one active region are laterally offset within a same level by the transition region to provide an offset space. The offset space includes a vertical interconnect.