Patents by Inventor James Patrick ROBERTSON

James Patrick ROBERTSON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9639466
    Abstract: One embodiment of the present invention sets forth a technique for processing commands received by an intermediary cache from one or more clients. The technique involves receiving a first write command from an arbiter unit, where the first write command specifies a first memory address, determining that a first cache line related to a set of cache lines included in the intermediary cache is associated with the first memory address, causing data associated with the first write command to be written into the first cache line, and marking the first cache line as dirty.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: May 2, 2017
    Assignee: NVIDIA Corporation
    Inventors: James Patrick Robertson, Gregory Alan Muthler, Hemayet Hossain, Timothy John Purcell, Karan Mehra, Peter B. Holmqvist, George R. Lynch
  • Patent number: 9110809
    Abstract: A method for managing memory traffic includes causing first data to be written to a data cache memory, where a first write request comprises a partial write and writes the first data to a first portion of the data cache memory, and further includes tracking the number of partial writes in the data cache memory. The method further includes issuing a fill request for one or more partial writes in the data cache memory if the number of partial writes in the data cache memory is greater than a predetermined first threshold.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: August 18, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Peter B. Holmqvist, Karan Mehra, George R. Lynch, James Patrick Robertson, Gregory Alan Muthler, Wishwesh Anil Gandhi, Nick Barrow-Williams
  • Publication number: 20150012705
    Abstract: A method for managing memory traffic includes causing first data to be written to a data cache memory, where a first write request comprises a partial write and writes the first data to a first portion of the data cache memory, and further includes tracking the number of partial writes in the data cache memory. The method further includes issuing a fill request for one or more partial writes in the data cache memory if the number of partial writes in the data cache memory is greater than a predetermined first threshold.
    Type: Application
    Filed: July 3, 2013
    Publication date: January 8, 2015
    Applicant: NVIDIA Corporation
    Inventors: Peter B. HOLMQVIST, Karan MEHRA, George R. LYNCH, James Patrick ROBERTSON, Gregory Alan MUTHLER, Wishwesh Anil GANDHI, Nick BARROW-WILLIAMS
  • Publication number: 20140136793
    Abstract: A system and method are described for dynamically changing the size of a computer memory such as level 2 cache as used in a graphics processing unit. In an embodiment, a relatively large cache memory can be implemented in a computing system so as to meet the needs of memory intensive applications. But where cache utilization is reduced, the capacity of the cache can be reduced. In this way, power consumption is reduced by powering down a portion of the cache.
    Type: Application
    Filed: November 13, 2012
    Publication date: May 15, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: James Patrick Robertson, Oren Rubinstein, Michael A. Woodmansee, Don Bittel, Stephen D. Lew, Edward Riegelsberger, Brad W. Simeral, Gregory Alan Muthler, John Matthew Burgess
  • Publication number: 20140122809
    Abstract: One embodiment of the present invention sets forth a technique for processing commands received by an intermediary cache from one or more clients. The technique involves receiving a first write command from an arbiter unit, where the first write command specifies a first memory address, determining that a first cache line related to a set of cache lines included in the intermediary cache is associated with the first memory address, causing data associated with the first write command to be written into the first cache line, and marking the first cache line as dirty.
    Type: Application
    Filed: October 30, 2012
    Publication date: May 1, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: James Patrick ROBERTSON, Gregory Alan MUTHLER, Hemayet HOSSAIN, Timothy John PURCELL, Karan MEHRA, Peter B. HOLMQVIST, George R. LYNCH