Abstract: An electrical device including a substrate, a dielectric layer supported by the substrate having at least one vertical post disposed within a via hole of the dielectric layer, and at least one electrically conductive vertical interconnect laterally offset from the post. The post is configured to impart a non-tensile state to a region of the electrical device underlying the post. The coefficient of thermal expansion (CTE) of the post may be configured to cooperate with the CTE of the dielectric layer to provide the non-tensile state, such as the dielectric layer having a CTE that is equal to or greater than a CTE of the post. The dielectric layer may have a CTE that is less than the CTE of the electrically conductive vertical interconnect, and may be arranged to provide a buffer to tensile forces imparted by the vertical interconnect.

Abstract: In one aspect, a method includes forming an electrical path between p-type mercury cadmium telluride and a metal layer. The forming of the electrical path includes depositing a layer of polycrystalline p-type silicon directly on to the p-type mercury cadmium telluride and forming the metal layer on the layer of polycrystalline p-type silicon. In another aspect, an apparatus includes an electrical path. The electrical path includes a p-type mercury cadmium telluride layer, a polycrystalline p-type silicon layer in direct contact with the p-type mercury cadmium telluride layer, a metal silicide in direct contact with the polycrystalline p-type silicon layer, and an electrically conductive metal on the metal silicide. In operation, holes, indicative of electrical current on the electrical path, flow from the p-type mercury cadmium telluride layer to the electrically conductive metal.

Abstract: A method of fabricating a semiconductor device includes implanting dopants into a silicon substrate, and performing a thermal anneal process that activates the implanted dopants. In response to activating the implanted dopants, a layer of ultra-thin single-crystal silicon is formed in a portion of the silicon substrate. The method further includes performing a heteroepitaxy process to grow a semiconductor material from the layer of ultra-thin single-crystal silicon.

Abstract: In one aspect, a method includes forming an electrical path between p-type mercury cadmium telluride and a metal layer. The forming of the electrical path includes depositing a layer of polycrystalline p-type silicon directly on to the p-type mercury cadmium telluride and forming the metal layer on the layer of polycrystalline p-type silicon. In another aspect, an apparatus includes an electrical path. The electrical path includes a p-type mercury cadmium telluride layer, a polycrystalline p-type silicon layer in direct contact with the p-type mercury cadmium telluride layer, a metal silicide in direct contact with the polycrystalline p-type silicon layer, and an electrically conductive metal on the metal silicide. In operation, holes, indicative of electrical current on the electrical path, flow from the p-type mercury cadmium telluride layer to the electrically conductive metal.

Abstract: An electrical device including a substrate, a dielectric layer supported by the substrate having at least one vertical post disposed within a via hole of the dielectric layer, and at least one electrically conductive vertical interconnect laterally offset from the post. The post is configured to impart a non-tensile state to a region of the electrical device underlying the post. The coefficient of thermal expansion (CTE) of the post may be configured to cooperate with the CTE of the dielectric layer to provide the non-tensile state, such as the dielectric layer having a CTE that is equal to or greater than a CTE of the post. The dielectric layer may have a CTE that is less than the CTE of the electrically conductive vertical interconnect, and may be arranged to provide a buffer to tensile forces imparted by the vertical interconnect.

Abstract: A method of fabricating a semiconductor device includes implanting dopants into a silicon substrate, and performing a thermal anneal process that activates the implanted dopants. In response to activating the implanted dopants, a layer of ultra-thin single-crystal silicon is formed in a portion of the silicon substrate. The method further includes performing a heteroepitaxy process to grow a semiconductor material from the layer of ultra-thin single-crystal silicon.

Abstract: A method of creating photolithographic masks for semiconductor device features with reduced design rule violations is provided. The method begins by providing preliminary data that represents an overall mask pattern. The preliminary data is processed to decompose the overall mask pattern into a plurality of component mask patterns. Next, a design rule check is performed on the plurality of component mask patterns to identify tip-to-tip and tip-to-line violations in the plurality of component mask patterns. The method continues by modifying at least one of the plurality of component mask patterns in accordance with the identified violations to obtain a modified set of component mask patterns, wherein each mask pattern in the modified set of component mask patterns is void of tip-to-tip and tip-to-line violations. Photolithographic masks are then created for the modified set of component mask patterns.

Abstract: A method of creating photolithographic masks for semiconductor device features with reduced design rule violations is provided. The method begins by providing preliminary data that represents an overall mask pattern. The preliminary data is processed to decompose the overall mask pattern into a plurality of component mask patterns. Next, a design rule check is performed on the plurality of component mask patterns to identify tip-to-tip and tip-to-line violations in the plurality of component mask patterns. The method continues by modifying at least one of the plurality of component mask patterns in accordance with the identified violations to obtain a modified set of component mask patterns, wherein each mask pattern in the modified set of component mask patterns is void of tip-to-tip and tip-to-line violations. Photolithographic masks are then created for the modified set of component mask patterns.