Abstract: A detector detects the end of a serial bit stream wherein the serial bit stream is based on one clock and the detector (and other associated circuitry) is based on a different, asynchronous clock. An Exclusive OR block receives the serial bit stream and a digital strobe signal according to IEEE High Performance Serial Bus Specification 1394. Based on this standard, one but not both of the serial bit stream and digital strobe signal changes level every data interval. The Exclusive OR block outputs a periodic signal when the serial bit stream and digital strobe signal are present but outputs a constant digital level upon termination of the serial bit stream and digital strobe signal. The detector also includes a first register coupled to receive the output of the receiver, a second register coupled to receive the output of the first register and a third register coupled to receive the output of the second register. All three registers are clocked simultaneously.

Abstract: A device converts serial data based on one clock to parallel data based on a different, asynchronous clock. The data converter comprises one register bank including first and second registers and another register bank including third and fourth registers. A data input of the first register and a data input of the third register are coupled to receive the serial data. A data input of the second register is coupled to a data output of the first register. A data input of the fourth register is coupled to a data output of the third register. A first clock triggers the first and second registers simultaneously and a second clock triggers the third and fourth registers simultaneously. The first and second clocks alternate with each other. Fifth, sixth, seventh and eighth registers have respective data inputs coupled to respective data outputs of the first, second, third and fourth registers.