Abstract: A method of testing semiconductor devices, the method includes the steps of making a first set of electrical connections to a first set of devices to allow a first set of tests to be performed on that set of devices and concurrently making a second set of electrical connections to a second set of devices to allow a second set of tests to be performed on the second set of devices, wherein the first and second sets of tests are different, and concurrently performing the first set of tests on the first set of devices and the second set of tests on the second set of devices.

Abstract: A method of testing semiconductor devices, the method includes the steps of making a first set of electrical connections to a first set of devices to allow a first set of tests to be performed on that set of devices and concurrently making a second set of electrical connections to a second set of devices to allow a second set of tests to be performed on the second set of devices, wherein the first and second sets of tests are different, and concurrently performing the first set of tests on the first set of devices and the second set of tests on the second set of devices.

Abstract: A method of making a circuitized substrate wherein a chip-accommodating cavity is formed along with a plurality of conductive elements (e.g., pads, lines, etc.) which form part of the substrate's circuitry. Metallization is facilitated by the use of a photoimageable member that allows for initial removal (peeling) of its sacrificial layer, followed by eventual removal of the photoimaging layer which also forms part of this member. Exposure of the photoimaging layer may occur either through the protective sacrificial layer or subsequent removal thereof.

Abstract: A method of making a circuitized substrate wherein a chip-accommodating cavity is formed along with a plurality of conductive elements (e.g., pads, lines, etc.) which form part of the substrate's circuitry. Metallization is facilitated by the use of a photoimageable member that allows for initial removal (peeling) of its sacrificial layer, followed by eventual removal of the photoimaging layer which also forms part of this member. Exposure of the photoimaging layer may occur either through the protective sacrificial layer or subsequent removal thereof.

Abstract: An improved method of making a circuitized substrate which may be utilized as a chip carrier structure. The method involves the steps of providing a dielectric member and partially routing this member to define a temporary support portion therein. Metallization and circuitization may then occur, following which the temporary support portion is removed, and at least one added layer of metallization is then applied to assure an entirely conductive opening between the member's opposing surfaces. The temporary support assures effective support for the dry film photoresist used as part of the circuitization process. Thus, the photoresist is capable of being applied in sheetlike form for spanning the relatively small openings of the dielectric without sagging, bowing, etc., which may adversely impact subsequent processing steps.