Patents by Inventor James Pfiester

James Pfiester has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8358548
    Abstract: A test system and a method for efficiently repairing marginally failing memory cells in an embedded dynamic random access memory on an integrated circuit identify marginally failing cells in the embedded memory and when two or more marginally failing cells are located in the same column, indicating a partial column failure due to a weak sense amplifier associated with the column, the system and method apply a spare column preferentially to repair the failing cells in the column. The test system can be arranged in a built-in self test engine on the integrated circuit. In an alternative embodiment, the test system can be implemented in test equipment coupled to the integrated circuit that houses the embedded dynamic random-access memory.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: January 22, 2013
    Assignee: Avago Technologies Enterprise IP (Singapore) Pte. Ltd.
    Inventors: Indrajit Manna, James Pfiester, David Leary
  • Publication number: 20110090751
    Abstract: A test system and a method for efficiently repairing marginally failing memory cells in an embedded dynamic random access memory on an integrated circuit identify marginally failing cells in the embedded memory and when two or more marginally failing cells are located in the same column, indicating a partial column failure due to a weak sense amplifier associated with the column, the system and method apply a spare column preferentially to repair the failing cells in the column The test system can be arranged in a built-in self test engine on the integrated circuit. In an alternative embodiment, the test system can be implemented in test equipment coupled to the integrated circuit that houses the embedded dynamic random-access memory.
    Type: Application
    Filed: October 19, 2009
    Publication date: April 21, 2011
    Applicant: Avago Technologies Enterprise IP (Singapore) Pte. Ltd.
    Inventors: Indrajit Manna, James Pfiester, David Leary
  • Publication number: 20060197623
    Abstract: A method and apparatus is presented for generating a reference voltage that biases a metal-oxide-semiconductor (MOS) transistor used as a varactor in capacitive tuning applications. In one embodiment, a biasing circuit is implemented. The biasing circuit comprises a diode-clamped FET and an element coupled to the diode-clamped FET at a connection point. The element produces a constant current through the diode-clamped FET. A voltage is produced at the connection point. The voltage is one gate overdrive plus a threshold voltage above ground or one gate overdrive plus a threshold voltage below VDD. Establishing a threshold voltage in this way enables the biasing circuit to track an ideal voltage of a varactor that is coupled to the biasing circuit through the threshold voltage.
    Type: Application
    Filed: March 3, 2005
    Publication date: September 7, 2006
    Inventors: Alvin Loke, Tin Wee, Robert Barnes, Kari Arave, Thomas Cynkar, James Pfiester