Patents by Inventor James Philip ALDIS

James Philip ALDIS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for using feedback information for selecting a routing bus for a memory transaction
    Patent number: 10402348
    Abstract: A method includes receiving feedback information indicative of an overload condition from an arbiter. The method further includes deprioritizing a routing bus based on the received feedback information and selecting a routing bus to use to send a transaction across a system-on-chip (SOC).
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: September 3, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: James Philip Aldis, Philippe Yvan Mestrallet
  • MEMORY INTERLEAVING ON MEMORY CHANNELS
    Publication number: 20160357666
    Abstract: A memory interleaver includes a channel selection unit to receive a system memory address for a memory request. The interleaver also includes a local memory address computation unit and a de-multiplexer. The channel selection unit examines a predetermined plurality (n) of bits in a memory address of a memory transaction and assigns the memory transaction to one of a plurality of memory channels in a multi-channel memory unit based on a state of the predetermined plurality of bits. Preferably, 2n is greater than the number of memory channels in the multi-channel memory unit.
    Type: Application
    Filed: August 23, 2016
    Publication date: December 8, 2016
    Inventors: Christophe Avoinne, James Philip Aldis, Vikas Sinha
  • MEMORY INTERLEAVING ON MEMORY CHANNELS
    Publication number: 20140310503
    Abstract: A memory interleaver includes a channel selection unit to receive a system memory address for a memory request. The interleaver also includes a local memory address computation unit and a de-multiplexer. The channel selection unit examines a predetermined plurality (n) of bits in a memory address of a memory transaction and assigns the memory transaction to one of a plurality of memory channels in a multi-channel memory unit based on a state of the predetermined plurality of bits. Preferably, 2n is greater than the number of memory channels in the multi-channel memory unit.
    Type: Application
    Filed: December 31, 2013
    Publication date: October 16, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Christophe AVOINNE, James Philip Aldis, Vikas SINHA
  • DYNAMIC BALANCING OF BUS BANDWIDTH ACROSS MULTIPLE ROUTES
    Publication number: 20140310444
    Abstract: A method includes receiving feedback information indicative of an overload condition from an arbiter. The method further includes deprioritizing a routing bus based on the received feedback information and selecting a routing bus to use to send a transaction across a system-on-chip (SOC).
    Type: Application
    Filed: November 25, 2013
    Publication date: October 16, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: James Philip ALDIS, Philippe Yvan MESTRALLET