Patents by Inventor James Pingenot

James Pingenot has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10586008
    Abstract: This application discloses a computing system configured to crop a layout design for an electronic device implemented with a layered interconnect, place a termination structure corresponding to a resistive sheet or a set of resistive components on an artificial boundary corresponding to an edge in the cropped portion of the layout design, and generate an electrical model of a signaling net in the cropped portion of the layout design by generating mesh elements on a surface area of the cropped portion of the layout design including the termination structure and utilizing a field solver implementing a Boundary Element Method based analysis to solve integral forms of Maxwell's equations corresponding to the mesh elements. The electrical model of the signaling net in the cropped portion of the layout design can include a set of scattering parameters for the signaling net in the cropped portion of the layout design.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: March 10, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Swagato Chakraborty, James Pingenot, Mosin Mondal
  • Publication number: 20180113971
    Abstract: This application discloses a computing system configured to crop a layout design for an electronic device implemented with a layered interconnect, place a termination structure corresponding to a resistive sheet or a set of resistive components on an artificial boundary corresponding to an edge in the cropped portion of the layout design, and generate an electrical model of a signaling net in the cropped portion of the layout design by generating mesh elements on a surface area of the cropped portion of the layout design including the termination structure and utilizing a field solver implementing a Boundary Element Method based analysis to solve integral forms of Maxwell's equations corresponding to the mesh elements. The electrical model of the signaling net in the cropped portion of the layout design can include a set of scattering parameters for the signaling net in the cropped portion of the layout design.
    Type: Application
    Filed: October 20, 2017
    Publication date: April 26, 2018
    Inventors: Swagato Chakraborty, James Pingenot, Mosin Modal
  • Patent number: 7644381
    Abstract: A method and system to efficiently create electromagnetic coupled basis functions for an electronic circuit that is defined by geometry data and topology data. The geometry data for the circuit are read, and a three-dimensional mesh of polygons for the circuit is created. External port geometry and internal port geometry (internal ports occur where vias are attached to conductive layers) are determined from the geometry data. Circuit electromagnetic basis functions are then created as are loop-tree formations that are coupled to the basis functions. The loops include local loops, via loops, and hole loops. The three-dimensional mesh is efficiently created by extruding a two-dimensional mesh for each layer and via in the circuit.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: January 5, 2010
    Assignee: University of Washington
    Inventors: Vikram Jandhyala, Swagato Chakraborty, James Pingenot
  • Publication number: 20070245275
    Abstract: A method and system to efficiently create electromagnetic coupled basis functions for an electronic circuit that is defined by geometry data and topology data. The geometry data for the circuit are read, and a three-dimensional mesh of polygons for the circuit is created. External port geometry and internal port geometry (internal ports occur where vias are attached to conductive layers) are determined from the geometry data. Circuit electromagnetic basis functions are then created as are loop-tree formations that are coupled to the basis functions. The loops include local loops, via loops, and hole loops. The three-dimensional mesh is efficiently created by extruding a two-dimensional mesh for each layer and via in the circuit.
    Type: Application
    Filed: April 17, 2007
    Publication date: October 18, 2007
    Applicant: University of Washington
    Inventors: Vikram Jandhyala, Swagato Chakraborty, James Pingenot