Patents by Inventor James Plusquellic

James Plusquellic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240089079
    Abstract: A side-channel attack countermeasure that leverages implementation diversity and dynamic partial reconfiguration as mechanisms to reduce correlation in the power traces measured during a differential power analysis (DPA) attack. The technique changes the underlying hardware implementation of any encryption algorithm using dynamic partial reconfiguration (DPR) to resist side-channel-based attacks.
    Type: Application
    Filed: November 18, 2023
    Publication date: March 14, 2024
    Inventor: James PLUSQUELLIC
  • Patent number: 11880468
    Abstract: The invention is directed to an autonomous, self-authenticating and self-contained secure boot-up system and methods for field programmable gate arrays (FPGAs) that leverages physical unclonable functions (PUFs).
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: January 23, 2024
    Assignee: UNM Rainforest Innovations
    Inventor: James Plusquellic
  • Patent number: 11863304
    Abstract: A side-channel attack countermeasure that leverages implementation diversity and dynamic partial reconfiguration as mechanisms to reduce correlation in the power traces measured during a differential power analysis (DPA) attack. The technique changes the underlying hardware implementation of any encryption algorithm using dynamic partial reconfiguration (DPR) to resist side-channel-based attacks.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: January 2, 2024
    Assignee: UNM RAINFOREST INNOVATIONS
    Inventor: James Plusquellic
  • Publication number: 20230216838
    Abstract: Authentication that leverages a Physical Unclonable Function (PUF) to generate bitstrings, session keys and long-lived keys (LLK).
    Type: Application
    Filed: June 2, 2021
    Publication date: July 6, 2023
    Inventors: James PLUSQUELLIC, Derek HEEGER
  • Patent number: 11411751
    Abstract: A privacy-preserving, mutual PUF-based authentication protocol that uses soft data to exchange and correlate Helper Data bitstrings instead of PUF response bitstrings as a means of authenticating chips to prevent attacks.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: August 9, 2022
    Inventors: James Plusquellic, Matt Areno
  • Publication number: 20210397415
    Abstract: This disclosure describes techniques for analyzing statistical quality of bitstrings produced by a physical unclonable function (PUF). The PUF leverages resistance variations in the power grid wires of an integrated circuit. Temperature and voltage stability of the bitstrings are analyzed. The disclosure also describes converting a voltage drop into a digital code, wherein the conversion is resilient to simple and differential side-channel attacks.
    Type: Application
    Filed: September 2, 2021
    Publication date: December 23, 2021
    Inventor: James Plusquellic
  • Publication number: 20210336805
    Abstract: The Distribution Effect is proposed for the HELP PUF that is based on purposely introducing biases in the mean and range parameters of path delay distributions to enhance entropy. The biased distributions are then used in the bitstring construction process to introduce differences in the bit values associated with path delays that would normally remain fixed. Offsets are computed to fine tune a token's digitized path delays as a means of maximizing entropy and reproducibility in the generated bitstrings: a first population-based offset method computes median values using data from multiple tokens (i.e., the population) and a second chip-specific technique is proposed which fine tunes path delays using enrollment data from the authenticating token.
    Type: Application
    Filed: July 8, 2021
    Publication date: October 28, 2021
    Inventors: James PLUSQUELLIC, Wenjie CHE
  • Patent number: 11132178
    Abstract: This disclosure describes techniques for analyzing statistical quality of bitstrings produced by a physical unclonable function (PUF). The PUF leverages resistance variations in the power grid wires of an integrated circuit. Temperature and voltage stability of the bitstrings are analyzed. The disclosure also describes converting a voltage drop into a digital code, wherein the conversion is resilient to simple and differential side-channel attacks.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: September 28, 2021
    Inventor: James Plusquellic
  • Patent number: 11095461
    Abstract: The Distribution Effect is proposed for the HELP PUF that is based on purposely introducing biases in the mean and range parameters of path delay distributions to enhance entropy. The biased distributions are then used in the bitstring construction process to introduce differences in the bit values associated with path delays that would normally remain fixed. Offsets are computed to fine tune a token's digitized path delays as a means of maximizing entropy and reproducibility in the generated bitstrings: a first population-based offset method computes median values using data from multiple tokens (i.e., the population) and a second chip-specific technique is proposed which fine tunes path delays using enrollment data from the authenticating token.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: August 17, 2021
    Inventors: James Plusquellic, Wenjie Che
  • Publication number: 20210135887
    Abstract: A privacy-preserving, mutual PUF-based authentication protocol that uses soft data to exchange and correlate Helper Data bitstrings instead of PUF response bitstrings as a means of authenticating chips to prevent attacks.
    Type: Application
    Filed: June 27, 2019
    Publication date: May 6, 2021
    Inventors: James PLUSQUELLIC, Matt ARENO
  • Patent number: 10956557
    Abstract: An authentication protocol using a Hardware-Embedded Delay PUF (“HELP”), which derives randomness from within-die path delay variations that occur along the paths within a hardware implementation of a cryptographic primitive, for example, the Advanced Encryption Standard (“AES”) algorithm or Secure Hash Algorithm 3 (“SHA-3”). The digitized timing values which represent the path delays are stored in a database on a secure server (verifier) as an alternative to storing PUF response bitstrings thereby enabling the development of an efficient authentication protocol that provides both privacy and mutual authentication.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: March 23, 2021
    Inventors: James Plusquellic, Wenjie Che, Dylan Ismari
  • Patent number: 10868535
    Abstract: A Hardware-Embedded Delay PUF (HELP) leverages entropy by monitoring path stability and measuring path delays from core logic macros. HELP incorporates techniques to deal with bias. A unique feature of HELP is that it may compare data measured from different test structures. HELP may be implemented in existing FPGA platforms. HELP may leverage both path stability and within-die variations as sources of entropy.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: December 15, 2020
    Assignee: STC.UNM
    Inventors: James Plusquellic, James Aarestad
  • Publication number: 20200342112
    Abstract: The invention is directed to an autonomous, self-authenticating and self-contained secure boot-up system and methods for field programmable gate arrays (FPGAs) that leverages physical unclonable functions (PUFs).
    Type: Application
    Filed: January 11, 2019
    Publication date: October 29, 2020
    Inventor: James PLUSQUELLIC
  • Publication number: 20200313847
    Abstract: A side-channel attack countermeasure that leverages implementation diversity and dynamic partial reconfiguration as mechanisms to reduce correlation in the power traces measured during a differential power analysis (DPA) attack. The technique changes the underlying hardware implementation of any encryption algorithm using dynamic partial reconfiguration (DPR) to resist side-channel-based attacks.
    Type: Application
    Filed: October 30, 2018
    Publication date: October 1, 2020
    Inventor: James PLUSQUELLIC
  • Publication number: 20200293288
    Abstract: This disclosure describes techniques for analyzing statistical quality of bitstrings produced by a physical unclonable function (PUF). The PUF leverages resistance variations in the power grid wires of an integrated circuit. Temperature and voltage stability of the bitstrings are analyzed. The disclosure also describes converting a voltage drop into a digital code, wherein the conversion is resilient to simple and differential side-channel attacks.
    Type: Application
    Filed: April 23, 2020
    Publication date: September 17, 2020
    Inventor: James Plusquellic
  • Publication number: 20200235735
    Abstract: A Hardware-Embedded Delay PUF (HELP) leverages entropy by monitoring path stability and measuring path delays from core logic macros. HELP incorporates techniques to deal with bias. A unique feature of HELP is that it may compare data measured from different test structures. HELP may be implemented in existing FPGA platforms. HELP may leverage both path stability and within-die variations as sources of entropy.
    Type: Application
    Filed: April 8, 2020
    Publication date: July 23, 2020
    Inventors: James Plusquellic, James Aarestad
  • Patent number: 10671350
    Abstract: This disclosure describes techniques for analyzing statistical quality of bitstrings produced by a physical unclonable function (PUF). The PUF leverages resistance variations in the power grid wires of an integrated circuit. Temperature and voltage stability of the bitstrings are analyzed. The disclosure also describes converting a voltage drop into a digital code, wherein the conversion is resilient to simple and differential side-channel attacks.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: June 2, 2020
    Assignee: STC.UNM
    Inventor: James Plusquellic
  • Patent number: 10666256
    Abstract: A Hardware-Embedded Delay PUF (HELP) leverages entropy by monitoring path stability and measuring path delays from core logic macros. HELP incorporates techniques to deal with bias. A unique feature of HELP is that it may compare data measured from different test structures. HELP may be implemented in existing FPGA platforms. HELP may leverage both path stability and within-die variations as sources of entropy.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: May 26, 2020
    Assignee: STC.UNM
    Inventors: James Plusquellic, James Aarestad
  • Publication number: 20190268170
    Abstract: The Distribution Effect is proposed for the HELP PUF that is based on purposely introducing biases in the mean and range parameters of path delay distributions to enhance entropy. The biased distributions are then used in the bitstring construction process to introduce differences in the bit values associated with path delays that would normally remain fixed. Offsets are computed to fine tune a token's digitized path delays as a means of maximizing entropy and reproducibility in the generated bitstrings: a first population-based offset method computes median values using data from multiple tokens (i.e., the population) and a second chip-specific technique is proposed which fine tunes path delays using enrollment data from the authenticating token.
    Type: Application
    Filed: November 3, 2017
    Publication date: August 29, 2019
    Inventors: James PLUSQUELLIC, Wenjie CHE
  • Patent number: 10366253
    Abstract: A Hardware-Embedded Delay Physical Unclonable Function (“HELP PUF”) leverages entropy by monitoring path stability and measuring path delays from core logic macros. Reliability and security enhancing techniques for the HELP PUF reduce bit flip errors during regeneration of the bitstring across environmental variations and improve cryptographic strength along with the corresponding difficulty of carrying out model building attacks. A voltage-based enrollment process screens unstable paths on normally synthesized (glitchy) functional units and reduces bit flip errors by carrying out enrollment at multiple supply voltages controlled using on-chip voltage regulators.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: July 30, 2019
    Assignee: STC.UNM
    Inventor: James Plusquellic