Abstract: A rain gutter paint sleeve made of a smooth, flexible polymer sleeve that is frictionally fit over an existing K-style gutter of various sizes from a K4 to a K6, prior to spray painting a house. It is designed with an inward biased front face provided by a front bottom corner formed at an acute angle. The sleeve frictionally contacts the rain gutter at the rear back corner, the bottom face front corner, the front face bottom corner and the front face. It is intended to be sold in four-foot lengths and in packages of four or five of these lengths. Its thickness will be much less than that of a conventional polymer rain gutter so that it can easily flex to fit over the various sizes of K-style gutters.

Abstract: A rain gutter paint sleeve made of a smooth, flexible polymer sleeve that is frictionally fit over an existing K-style gutter of various sizes from a K4 to a K6, prior to spray painting a house. It is designed with an inward biased front face provided by a front bottom corner formed at an acute angle. The sleeve frictionally contacts the rain gutter at the rear back corner, the bottom face front corner, the front face bottom corner and the front face. It is intended to be sold in four-foot lengths and in packages of four or five of these lengths. Its thickness will be much less than that of a conventional polymer rain gutter so that it can easily flex to fit over the various sizes of K-style gutters.

Abstract: A serial peripheral interface (SPI) host port is disclosed that enables a host external to a processor to access the processor's memory-mapped resources using SPI memory command protocol. An exemplary processor can include a system interconnect connected to memory-mapped resources and a SPI host port connected to the system interconnect. The SPI host port is configured to use SPI memory command protocol to access memory-mapped resources of the processor for the host external to the processor.

Abstract: A data processing chip with a flexible timing system and method for supplying clocks to a digital data processing system useful for power conservation. A phase locked loop generates a master clock from which a core clock and a system clock are derived. The frequency of each of the core and system clocks is independently controllable relative to the master clock and can be changed on the fly with glitch free and jitter free operation. The data processing chip is well suited for use in hand held electronic devices where power management is a concern. Power can be saved by lowering the frequency of the core clock, even for short intervals of time.