Abstract: A signal processing system (10) is described which has a processor (12), a random access memory (14) for storage of data, a read-only memory (16) for storage of both coefficients and instructions, and a selective cache memory (18) for storage of instructions that require high performance, and their associated buses. Instructions selected by the program are stored in the selective cache memory during their first call from the read only memory for use later in the program. An address sequencer (50) is described as one form of a control unit for executing the data stored in the selective cache memory. It generates a sequence of addresses repetitively, counts the number of iterations of the sequence of addresses, and informs the controller when a certain number of iterations have been completed. This creates a conditional branch statement in the program of the signal processing system (10).

Abstract: A pipelined digital signal processor includes a common data and control bus (101) and a source (100,105) of instructions and data words. An arithmetic section (110) processes one data word with another data word through selected processing subsections performing operations according to an expression, thereby producing a resultant data word. A destination (105) receives the resultant data word from the arithmetic section. Control circuits (IR-L,M,N and IR-S,T) receive a single instruction (i.e., I.sub.i) during each processor cycle for controlling all processing subsections (112, 115, 116) operations. During each processor cycle, each processing subsection (i.e., 112) performs an operation relating to a different expression than the other processing subsections (i.e., 115 or 116) are performing during that processor cycle. All of the operations controlled by the single instruction (i.e., I.sub.i) are executed during a single processor cycle.

Abstract: A pipelined digital processor includes a common data and control bus and a source (100 or 105) of instructions and data words. An arithmetic section (110) processes one data word with another data word through selected processing subsections (112, 115, 116) performing operations according to an expression, thereby producing a resultant data word and a status signal. A destination (105) receives the resultant data word from the arithmetic section. Control circuits (IR-C) decode a single conditional instruction for controlling performance of a specific condition test during a first subsequent processor cycle (i.e., i+2). The control circuits further decoding another instruction word during the first subsequent processor cycle for controlling all processing sections operations during a second subsequent processor cycle (i.e., i+3).