Patents by Inventor James R. Clarke

James R. Clarke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200295164
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer; a first gate above the quantum well stack, wherein the first gate includes a first gate metal; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal, and a material structure of the second gate metal is different from a material structure of the first gate metal; wherein the quantum well layer has a first strain under the first gate, a second strain under the second gate, and the first strain is different from the second strain.
    Type: Application
    Filed: January 8, 2018
    Publication date: September 17, 2020
    Applicant: Intel Corporation
    Inventors: Kanwaljit Singh, Ravi Pillarisetty, Nicole K. Thomas, Payam Amin, Roman Caudillo, Hubert C. George, Jeanette M. Roberts, Zachary R. Yoscovits, James S. Clarke, Lester Lampert, David J. Michalak
  • Publication number: 20200279937
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include a quantum well stack, the quantum well stack includes a quantum well layer, the quantum processing device further includes a plurality of gates above the quantum well stack to control quantum dot formation in the quantum well stack, and (1) gate metal of individual gates of the array of gates is tapered so as to narrow farther from the quantum well stack or (2) top surfaces of gate metal of individual gates of the array of gates are dished.
    Type: Application
    Filed: December 23, 2017
    Publication date: September 3, 2020
    Applicant: Intel Corporation
    Inventors: Ravi Pillarisetty, Willy Rachmady, Kanwaljit Singh, Nicole K. Thomas, Hubert C. George, Zachary R. Yoscovits, Roman Caudillo, Payam Amin, Jeanette M. Roberts, James S. Clarke
  • Patent number: 10763349
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, a doped layer, and a barrier layer disposed between the doped layer and the quantum well layer; and gates disposed above the quantum well stack. The doped layer may include a first material and a dopant, the first material may have a first diffusivity of the dopant, the barrier layer may include a second material having a second diffusivity of the dopant, and the second diffusivity may be less than the first diffusivity.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Van H. Le, Jeanette M. Roberts, James S. Clarke, Zachary R. Yoscovits, David J. Michalak
  • Patent number: 10763347
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include: a quantum well stack having alternatingly arranged relaxed and strained layers; and a plurality of gates disposed above the quantum well stack to control quantum dot formation in the quantum well stack.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Payam Amin, Nicole K. Thomas, James S. Clarke, Jessica M. Torres, Ravi Pillarisetty, Hubert C. George, Kanwaljit Singh, Van H. Le, Jeanette M. Roberts, Roman Caudillo, Zachary R. Yoscovits, David J. Michalak
  • Patent number: 10758931
    Abstract: Methods and apparatuses for applying liquid coatings are provided. A first roll (14), a second roll (16), and a nip (146) formed between the first and second rolls are provided. A coating liquid (22) is supplied to the nip. The coating liquid is smoothed, via the nip, into a substantially uniform layer (22a) of liquid coating which is transferred to a substrate (12). The second roll (16) includes a thin metal shell (40) and a resilient layer (30), the thin metal shell encases the resilient layer therebeneath, and the thin metal shell is capable of deflecting in unison with the resilient layer such that the thin metal shell is elastically deformable at the nip when in contact with the first roll (14).
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: September 1, 2020
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Shawn C. Dodds, Mikhail L. Pekurovsky, James N. Dobbs, Graham M. Clarke, Michele A. Craton, Adam W. Kiefer, Matthew R. D. Smith, Brian E. Schreiber
  • Patent number: 10763420
    Abstract: Described herein are structures that include Josephson Junctions (JJs) to be used in superconducting qubits of quantum circuits disposed on a substrate. The JJs of these structures are fabricated using an approach that can be efficiently used in large scale manufacturing, providing a substantial improvement with respect to conventional approaches which include fabrications steps which are not manufacturable. In one aspect of the present disclosure, the proposed approach includes providing a patterned superconductor layer over a substrate, providing a layer of surrounding dielectric over the patterned superconductor layer, and providing a via opening in the layer of surrounding dielectric over a first portion of the patterned superconductor layer. The proposed approach further includes depositing in the via opening a first superconductor, a barrier dielectric, and a second superconductor to form, respectively, a base electrode, a tunnel barrier layer, and a top electrode of the JJ.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Zachary R. Yoscovits, David J. Michalak, Jeanette M. Roberts, Ravi Pillarisetty, James S. Clarke
  • Patent number: 10756202
    Abstract: Disclosed herein are quantum dot device packages, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device package may include a die having a quantum dot device, wherein the quantum dot device includes a quantum well stack, gates disposed above the quantum well stack, and conductive pathways coupled between associated ones of the gates and conductive contacts of the die. The quantum dot device package may also include a package substrate, wherein conductive contacts are disposed on the package substrate, and first level interconnects are disposed between the die and the package substrate, coupling the conductive contacts of the die with associated conductive contacts of the package substrate.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Jeanette M. Roberts, Ravi Pillarisetty, David J. Michalak, Zachary R. Yoscovits, James S. Clarke, Adel A. Elsherbini
  • Patent number: 10748961
    Abstract: Described herein are structures that include interconnects for providing electrical connectivity in superconducting quantum circuits. One structure includes a first and a second interconnects provided over a surface of an interconnect support layer, e.g. a substrate, on which superconducting qubits are provided, a lower interconnect provided below such surface (i.e. below-plane interconnect), and vias for providing electrical interconnection between the lower interconnect and each of the first and second interconnects. Providing below-plane interconnects in superconducting quantum circuits allows realizing superconducting and mechanically stable interconnects. Implementing below-plane interconnects by bonding of two substrates, material for which could be selected, allows minimizing the amount of spurious two-level systems in the areas surrounding below-plane interconnects while allowing different choices of materials to be used. Methods for fabricating such structures are disclosed as well.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 18, 2020
    Assignee: Intel Corporation
    Inventors: David J. Michalak, Ravi Pillarisetty, Zachary R. Yoscovits, Jeanette M. Roberts, James S. Clarke
  • Patent number: 10748960
    Abstract: Described herein are structures that include interconnects for providing electrical connectivity in superconducting quantum circuits. In one aspect of the present disclosure, a structure includes a first and a second interconnects provided over a surface of an interconnect support layer on which superconducting qubits are provided (which could be a substrate), a lower interconnect provided below such surface, and vias for providing electrical interconnection between the lower interconnect and each of the first and second interconnects. The lower interconnect includes a material of the interconnect support layer doped to be superconductive. Providing below-plane interconnects in superconducting quantum circuits allows realizing superconducting and mechanically stable interconnects. Implementing below-plane interconnects by doping the interconnect support layer, material for which could be selected, allows minimizing the amount of spurious TLS's in the areas surrounding below-plane interconnects.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 18, 2020
    Assignee: Intel Corporation
    Inventors: David J. Michalak, Jeanette M. Roberts, Ravi Pillarisetty, Zachary R. Yoscovits, James S. Clarke
  • Patent number: 10734482
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; and one or more gates disposed on the fin. In some such embodiments, the one or more gates may include first, second, and third gates. Spacers may be disposed on the sides of the first and second gates, such that a first spacer is disposed on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is disposed on a side of the second gate proximate to the first gate. The third gate may be disposed on the fin between the first and second gates and extend between the first and second spacers.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Jeanette M. Roberts, Ravi Pillarisetty, David J. Michalak, Zachary R. Yoscovits, James S. Clarke
  • Patent number: 10714604
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; a first dielectric material around a bottom portion of the fin; and a second dielectric material around a top portion of the fin, wherein the second dielectric material is different from the first dielectric material.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: July 14, 2020
    Assignee: Intel Corporation
    Inventors: Hubert C. George, David J. Michalak, Ravi Pillarisetty, Lester Lampert, James S. Clarke, Zachary R. Yoscovits, Nicole K. Thomas, Roman Caudillo, Kanwaljit Singh, Jeanette M. Roberts
  • Publication number: 20200212210
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; an insulating material at least partially above the fin, wherein the insulating material includes a trench above the fin; and a gate metal on the insulating material and extending into the trench.
    Type: Application
    Filed: December 21, 2017
    Publication date: July 2, 2020
    Applicant: Intel Corporation
    Inventors: Ravi Pillarisetty, Nicole K. Thomas, Hubert C. George, Jeanette M. Roberts, Payam Amin, Zachary R. Yoscovits, Roman Caudillo, James S. Clarke
  • Patent number: 10697357
    Abstract: Cross-port air flow that improves engine fuel economy and reduces pumping losses during part-throttle operation can be implemented in various types of internal combustion engine systems using ports that interconnect the intake ports of different cylinders, thus allowing different cylinders to share combustion air. Cross-port air flow is commenced during part-throttle engine operation to disrupt the primary combustion air flow from each throttle to its associated cylinder, which reduces charge density and engine power. The engine compensates for the reduced power by incrementally opening the throttles, thus increasing the primary combustion air flow, reducing pumping losses and improving fuel economy.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: June 30, 2020
    Assignee: Bright Acceleration Technologies LLC
    Inventors: James R. Clarke, Richard J. Fotsch, C. Thomas Sylke
  • Patent number: 10695629
    Abstract: Golf club heads with cavities and inserts, and methods to manufacture golf club heads with cavities. Various embodiments include a golf club head comprising a body. The body comprises a strikeface at a front of the golf club head, a backface opposite the strikeface, a heel region, a toe region opposite the heel region, a sole, a rear portion at a rear of the golf club head, and a cavity located between the backface and the rear portion. In many embodiments, the body further comprises an insert within the cavity.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: June 30, 2020
    Assignee: Karsten Manufacturing Corporation
    Inventors: David L. Petersen, Les J. Bryant, James D. Glover, Richard D. MacMillan, Xiaojian Chen, Martin R. Jertson, Yujen Huang, Jacob T. Clarke, Tyler A. Shaw, William D. Shearer, Travis D. Milleman
  • Publication number: 20200203593
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate and a quantum well stack disposed on the substrate. The quantum well stack may include a quantum well layer and a back gate, and the back gate may be disposed between the quantum well layer and the substrate.
    Type: Application
    Filed: June 9, 2016
    Publication date: June 25, 2020
    Applicant: Intel Corporation
    Inventors: Jeanette M. Roberts, Ravi Pillarisetty, David J. Michalak, Zachary R. Yoscovits, James S. Clarke, Van H. Le
  • Publication number: 20200198859
    Abstract: A container (210) for holding granular or powdered material and formed by a top wall (212), a bottom wall (214), a front wall (216), a rear wall (218), a first side wall (220), and a second side wall (222). A rotatably removable lid (D) is interiorly mounted with a scoop (32) and is pivotally hinged to a collar (300) that includes a sealing gasket (330). The collar (300) mounts to the walls of the container (210). A sealing wall 240 of the lid (D) cooperates with the gasket 300 to prevent the contents from spilling. The container (210) incorporates powder control features, a container wall junction (50) preferred geometry and congruent scoop (32) enabling convenient access to the contents, a tolerance variation accommodating and strength improving, J-shaped collar (300) and interlocking indentations (290) and flex clips (310), and a pressure controlling portion (350) that prevents unwanted deformation due to pressure differentials.
    Type: Application
    Filed: March 2, 2020
    Publication date: June 25, 2020
    Applicant: ABBOTT LABORATORIES
    Inventors: JAMES P. PERRY, CRAIG A. MCCARDELL, JEREMY MCBROOM, DAVID COMPEAU, ASHLEY A. GOHLKE, WILLIAM J. HOOK, KATHERINE J. JORDAN, FRANK S. WALCZAK, PETER B. CLARKE, J. KEVIN CLAY, RICHARD C. DARR, JACK E. ELDER, MARC A. PEDMO, CHARLES R. SCHOTTHOEFER
  • Patent number: 10686007
    Abstract: Embodiments of the present disclosure propose quantum circuit assemblies with transmission lines and/or capacitors that include layer-conductors oriented perpendicular to a substrate (i.e. oriented vertically) or a qubit die, with at least portions of the vertical layer-conductors being at least partially buried in the substrate. Such layer-conductors may form ground and signal planes of transmission lines or capacitor plates of capacitors of various quantum circuit assemblies.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Hubert C. George, Adel A. Elsherbini, Lester Lampert, James S. Clarke, Ravi Pillarisetty, Zachary R. Yoscovits, Nicole K. Thomas, Roman Caudillo, Kanwaljit Singh, David J. Michalak, Jeanette M. Roberts
  • Publication number: 20200164610
    Abstract: Various embodiments disclosed relate to an article. The article includes a first layer defining a first major surface of the article. The first layer includes a plurality of protrusions extending outwardly from the first major surface. The protrusions comprise an elastic polymer component. The article further includes a second layer opposite the first layer, which at least partially defines a second major surface of the article. The first layer is disposed over a range of about 5% surface area of the second layer to about 99% surface area of the second layer. The first layer and the second layer are in direct contact.
    Type: Application
    Filed: May 4, 2018
    Publication date: May 28, 2020
    Inventors: Douglas A. Davis, Paul D. Graham, James J. Kobe, Thomas B. Galush, Graham M. Clarke, Thomas E. Pahl, Charles R. Wald, Brian W. Lueck, John G. Petersen
  • Patent number: 10665770
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; a gate above the fin; and a material on side faces of the fin; wherein the fin has a width between its side faces, and the fin is strained in the direction of the width.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Kanwaljit Singh, Patrick H. Keys, Roman Caudillo, Hubert C. George, Zachary R. Yoscovits, Nicole K. Thomas, James S. Clarke, Roza Kotlyar, Payam Amin, Jeanette M. Roberts
  • Patent number: 10665769
    Abstract: Various embodiments of the present disclosure present quantum circuit assemblies implementing vertically-stacked parallel-plate capacitors. Such capacitors include first and second capacitor plates which are parallel to one another and separated from one another by a gap measured along a direction perpendicular to the qubit plane, i.e. measured vertically. Fabrication techniques for manufacturing such capacitors are also disclosed. Vertically-stacked parallel-plate capacitors may help increasing coherence times of qubits, facilitate use of three-dimensional and stacked designs for quantum circuit assemblies, and may be particularly advantageous for realizing device scalability and use of 300-millimeter fabrication processes.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Roman Caudillo, Zachary R. Yoscovits, Lester Lampert, David J. Michalak, Jeanette M. Roberts, Ravi Pillarisetty, Hubert C. George, Nicole K. Thomas, James S. Clarke