Patents by Inventor James R. Feddeler
James R. Feddeler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10164426Abstract: An integrated circuit includes an I/O pad and a protection device coupled to the I/O pad and a first supply node. A transient event detector includes a latch; a first transistor having a first current electrode coupled to the I/O pad, a control electrode coupled to a first supply node, and a second current electrode coupled to a data input of the latch, wherein the latch is configured to store an indication that a transient event occurred. An event level sensor includes a first transistor having a first current electrode coupled to the I/O pad, a control electrode coupled to the protection device, and a second current electrode coupled to a load circuit; a rectifier device coupled between the second current electrode and a capacitor; a second transistor having a control electrode coupled to the capacitor; and an output circuit configured to place a current on a first sense bus proportional to a current through the load circuit.Type: GrantFiled: May 27, 2016Date of Patent: December 25, 2018Assignee: NXP USA, Inc.Inventors: Michael A. Stockinger, Gregory C. Edgington, James R. Feddeler, Xiang Li, Richard W. Moseley, Mihir Suchak
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Patent number: 9898625Abstract: A method and apparatus for limiting access to an integrated circuit (IC) upon detection of abnormal conditions is provided. At least one of abnormal voltage detection, abnormal temperature detection, and abnormal clock detection are provided with low power consumption. Both abnormally low and abnormally high parameter values (e.g. abnormally low or high voltage, temperature, or clock frequency) may be detected. Abnormal clock detection may also detect a stopped clock signal, including a clock signal stopped at a low logic level or at a high logic level. Furthermore, abnormal clock detection may detect an abnormal duty cycle of a clock signal. A sampled bandgap reference may be used to provide accurate voltage and current references while consuming a minimal amount of power. Upon detection of an abnormal parameter value, one or more tamper indications may be provided to initiate tampering countermeasures, such as limiting access to the IC.Type: GrantFiled: June 1, 2015Date of Patent: February 20, 2018Assignee: NXP USA, INC.Inventors: Alfredo Olmos, James R. Feddeler, Miten H. Nagda, Stefano Pietri
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Publication number: 20170346280Abstract: An integrated circuit includes an I/O pad and a protection device coupled to the I/O pad and a first supply node. A transient event detector includes a latch; a first transistor having a first current electrode coupled to the I/O pad, a control electrode coupled to a first supply node, and a second current electrode coupled to a data input of the latch, wherein the latch is configured to store an indication that a transient event occurred. An event level sensor includes a first transistor having a first current electrode coupled to the I/O pad, a control electrode coupled to the protection device, and a second current electrode coupled to a load circuit; a rectifier device coupled between the second current electrode and a capacitor; a second transistor having a control electrode coupled to the capacitor; and an output circuit configured to place a current on a first sense bus proportional to a current through the load circuit.Type: ApplicationFiled: May 27, 2016Publication date: November 30, 2017Inventors: Michael A. STOCKINGER, Gregory C. EDGINGTON, James R. FEDDELER, Xiang LI, Richard W. MOSELEY, Mihir SUCHAK
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Patent number: 9197231Abstract: Systems and methods for electronically converting an analog signal to a digital signal are disclosed. The systems and methods may include, for a first bit value, setting a first conversion value to include a first offset; using the output of a first comparison, setting a second conversion value; and if the first bit value has a predetermined relationship to the first offset bit value, removing the first offset from the second conversion value, and, using the output of a second comparison, setting a third conversion value.Type: GrantFiled: April 30, 2014Date of Patent: November 24, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: James R. Feddeler, Michael T. Berens
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Publication number: 20150318862Abstract: Systems and methods for electronically converting an analog signal to a digital signal are disclosed. The systems and methods may include, for a first bit value, setting a first conversion value to include a first offset; using the output of a first comparison, setting a second conversion value; and if the first bit value has a predetermined relationship to the first offset bit value, removing the first offset from the second conversion value, and, using the output of a second comparison, setting a third conversion value.Type: ApplicationFiled: April 30, 2014Publication date: November 5, 2015Inventors: James R. Feddeler, Michael T. Berens
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Publication number: 20150317496Abstract: A method and apparatus for limiting access to an integrated circuit (IC) upon detection of abnormal conditions is provided. At least one of abnormal voltage detection, abnormal temperature detection, and abnormal clock detection are provided with low power consumption. Both abnormally low and abnormally high parameter values (e.g. abnormally low or high voltage, temperature, or clock frequency) may be detected. Abnormal clock detection may also detect a stopped clock signal, including a clock signal stopped at a low logic level or at a high logic level. Furthermore, abnormal clock detection may detect an abnormal duty cycle of a clock signal. A sampled bandgap reference may be used to provide accurate voltage and current references while consuming a minimal amount of power. Upon detection of an abnormal parameter value, one or more tamper indications may be provided to initiate tampering countermeasures, such as limiting access to the IC.Type: ApplicationFiled: June 1, 2015Publication date: November 5, 2015Inventors: Alfredo Olmos, James R. Feddeler, Miten H. Nagda, Stefano Pietri
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Patent number: 9046570Abstract: A method and apparatus for limiting access to an integrated circuit (IC) upon detection of abnormal conditions is provided. At least one of abnormal voltage detection, abnormal temperature detection, and abnormal clock detection are provided with low power consumption. Both abnormally low and abnormally high parameter values (e.g. abnormally low or high voltage, temperature, or clock frequency) may be detected. Abnormal clock detection may also detect a stopped clock signal, including a clock signal stopped at a low logic level or at a high logic level. Furthermore, abnormal clock detection may detect an abnormal duty cycle of a clock signal. A sampled bandgap reference may be used to provide accurate voltage and current references while consuming a minimal amount of power. Upon detection of an abnormal parameter value, one or more tamper indications may be provided to initiate tampering countermeasures, such as limiting access to the IC.Type: GrantFiled: August 3, 2012Date of Patent: June 2, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Alfredo Olmos, James R. Feddeler, Miten H. Nagda, Stefano Pietri
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Patent number: 9030346Abstract: A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.Type: GrantFiled: May 24, 2013Date of Patent: May 12, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Sanjoy K. Dey, Michael T. Berens, James R. Feddeler, Vikram Varma
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Publication number: 20140035560Abstract: A method and apparatus for limiting access to an integrated circuit (IC) upon detection of abnormal conditions is provided. At least one of abnormal voltage detection, abnormal temperature detection, and abnormal clock detection are provided with low power consumption. Both abnormally low and abnormally high parameter values (e.g. abnormally low or high voltage, temperature, or clock frequency) may be detected. Abnormal clock detection may also detect a stopped clock signal, including a clock signal stopped at a low logic level or at a high logic level. Furthermore, abnormal clock detection may detect an abnormal duty cycle of a clock signal. A sampled bandgap reference may be used to provide accurate voltage and current references while consuming a minimal amount of power. Upon detection of an abnormal parameter value, one or more tamper indications may be provided to initiate tampering countermeasures, such as limiting access to the IC.Type: ApplicationFiled: August 3, 2012Publication date: February 6, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Alfredo Olmos, James R. Feddeler, Miten H. Nagda, Stefano Pietri
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Patent number: 8643410Abstract: A system for compensating for variations in the frequency of an input clock signal having a first frequency includes a coarse counter that receives the input clock signal, counts a predetermined number of clock pulses of the input clock signal, and generates a coarse compensated clock signal having a second frequency. A first compensation module adjusts a clock pulse of the input clock signal based on a coarse compensation value. A residual period adjustment module accumulates a fine compensation value for each clock pulse of the coarse compensated clock signal. A fine counter operates at a third frequency of a fine clock signal, receives an adjusted delay value based on the accumulated fine compensation value, counts a number of fine clock pulses in each clock pulse of the coarse compensated clock signal, and generates a fine compensated clock signal having the second frequency.Type: GrantFiled: September 2, 2012Date of Patent: February 4, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Prashant Bhargava, Mohit Arora, James R. Feddeler, Martin Mienkina
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Publication number: 20130249723Abstract: A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.Type: ApplicationFiled: May 24, 2013Publication date: September 26, 2013Inventors: Sanjoy K. Dey, Michael T. Berens, James R. Feddeler, Vikram Varma
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Patent number: 8477052Abstract: A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.Type: GrantFiled: April 5, 2011Date of Patent: July 2, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Sanjoy K. Dey, Michael T. Berens, James R. Feddeler, Vikram Varma
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Patent number: 8319550Abstract: A programmable-gain amplifier has a first input node coupled to receive a first input signal and a control input coupled to receive a gain select signal. The programmable-gain amplifier includes a differential amplifier having a first input and a first output and a plurality of capacitors. A first terminal of each of the plurality of capacitors is coupled to the first input of the differential amplifier, and a second terminal of each of the plurality of capacitors is coupled to the first input node during a sampling phase of the programmable-gain amplifier and selectively coupled to the first output of the differential amplifier, based on the gain select signal, during a gain phase of the programmable-gain amplifier.Type: GrantFiled: January 18, 2011Date of Patent: November 27, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Ammisetti V. Prasad, James R. Feddeler
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Publication number: 20120256774Abstract: A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.Type: ApplicationFiled: April 5, 2011Publication date: October 11, 2012Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Sanjoy K. Dey, Michael T. Berens, James R. Feddeler, Vikram Varma
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Patent number: 8278960Abstract: A measurement circuit and method for measuring a quiescent current of a circuit under test are provided. The measurement circuit comprises: a comparator having a first input terminal for receiving a reference voltage, a second input terminal coupled to the circuit under test, and an output terminal; a current source having a first terminal coupled to a first power supply voltage terminal, and a second terminal for providing a current to the circuit under test; a first switch having a first terminal coupled to the second terminal of the current source, a second terminal coupled to the circuit under test, and a control terminal coupled to the output terminal of the comparator; and a first counter having a first input terminal coupled to the output terminal of the comparator, a second input terminal for receiving a clock signal, and an output terminal for providing a first counter value associated with the quiescent current.Type: GrantFiled: June 19, 2009Date of Patent: October 2, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Dale J. McQuirk, Michael T. Berens, James R. Feddeler
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Publication number: 20120182067Abstract: A programmable-gain amplifier has a first input node coupled to receive a first input signal and a control input coupled to receive a gain select signal. The programmable-gain amplifier includes a differential amplifier having a first input and a first output and a plurality of capacitors. A first terminal of each of the plurality of capacitors is coupled to the first input of the differential amplifier, and a second terminal of each of the plurality of capacitors is coupled to the first input node during a sampling phase of the programmable-gain amplifier and selectively coupled to the first output of the differential amplifier, based on the gain select signal, during a gain phase of the programmable-gain amplifier.Type: ApplicationFiled: January 18, 2011Publication date: July 19, 2012Inventors: Ammisetti V. Prasad, James R. Feddeler
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Patent number: 7880650Abstract: A data converter for converting analog signals to digital signals, or for converting digital signals to analog signals is provided. In one embodiment, a production self-test is provided. In one embodiment, a high-speed lower-resolution method or mode for a data converter is provided. In one embodiment, a differential data converter with a more stable comparator common mode voltage is provided. In one embodiment, the input range of a digitally calibrated data converter is provided and maintained so that there is no loss in input range due to the calibration. In one embodiment, digital post-processing of an uncalibrated result using a previously stored calibration value is provided.Type: GrantFiled: September 30, 2008Date of Patent: February 1, 2011Assignee: Freescale Semiconductor, Inc.Inventors: James R. Feddeler, Michael T. Berens
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Patent number: 7876254Abstract: A data converter for converting analog signals to digital signals, or for converting digital signals to analog signals is provided. In one embodiment, a production self-test is provided. In one embodiment, a high-speed lower-resolution method or mode for a data converter is provided. In one embodiment, a differential data converter with a more stable comparator common mode voltage is provided. In one embodiment, the input range of a digitally calibrated data converter is provided and maintained so that there is no loss in input range due to the calibration. In one embodiment, digital post-processing of an uncalibrated result using a previously stored calibration value is provided.Type: GrantFiled: September 30, 2008Date of Patent: January 25, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Michael T. Berens, James R. Feddeler
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Patent number: 7868795Abstract: A data converter for converting analog signals to digital signals, or for converting digital signals to analog signals is provided. In one embodiment, a production self-test is provided. In one embodiment, a high-speed lower-resolution method or mode for a data converter is provided. In one embodiment, a differential data converter with a more stable comparator common mode voltage is provided. In one embodiment, the input range of a digitally calibrated data converter is provided and maintained so that there is no loss in input range due to the calibration. In one embodiment, digital post-processing of an uncalibrated result using a previously stored calibration value is provided.Type: GrantFiled: September 30, 2008Date of Patent: January 11, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Michael T. Berens, James R. Feddeler
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Patent number: 7868796Abstract: A data converter for converting analog signals to digital signals, or for converting digital signals to analog signals is provided. In one embodiment, a production self-test is provided. In one embodiment, a high-speed lower-resolution method or mode for a data converter is provided. In one embodiment, a differential data converter with a more stable comparator common mode voltage is provided. In one embodiment, the input range of a digitally calibrated data converter is provided and maintained so that there is no loss in input range due to the calibration. In one embodiment, digital post-processing of an uncalibrated result using a previously stored calibration value is provided.Type: GrantFiled: September 30, 2008Date of Patent: January 11, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Michael T. Berens, James R. Feddeler