Patents by Inventor James R. Gardiner

James R. Gardiner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4437108
    Abstract: A contact structure in a double polysilicon device is described in which direct shorts between overlying polysilicon conductors due to a "polysilicon void phenomenon" is overcome by patterning an appropriate etch stop between the conductors.
    Type: Grant
    Filed: December 20, 1982
    Date of Patent: March 13, 1984
    Assignee: International Business Machines Corporation
    Inventors: James R. Gardiner, Stanley R. Makarewicz, Martin Revitz, Joseph F. Shepard
  • Patent number: 4394406
    Abstract: A contact structure in a double polysilicon device is described in which direct shorts between overlying polysilicon conductors due to a "polysilicon void phenomenon" is overcome by patterning an appropriate etch stop between the conductors.
    Type: Grant
    Filed: June 30, 1980
    Date of Patent: July 19, 1983
    Assignee: International Business Machines Corp.
    Inventors: James R Gardiner, Stanley R. Makarewicz, Martin Revitz, Joseph F. Shepard
  • Patent number: 4354309
    Abstract: A method of making a metal-oxide-semiconductor device is disclosed. A thin silicon dioxide insulating layer is formed on the surface of a planar silicon wafer. A first layer of intrinsic polycrystalline silicon is deposited over the dioxide layer, and a second layer of doped polycrystalline silicon is deposited over the intrinsic layer, thereby forming the gate. Subsequent hot processing steps result in diffusion of a portion of the dopant from the doped polycrystalline layer into and throughout the intrinsic layer so as to dope the latter. A metal contact layer is then deposited onto the gate and in superimposed vertical alignment with respect to the thin silicon dioxide insulating layer. The intrinsic nature of the first polycrystalline layer reduces grain growth and void formation in the polycrystalline silicon and thereby prevents the silicon dioxide from being attacked by hydrofluoric acid seeping through voids in the polycrystalline layer during subsequent processing.
    Type: Grant
    Filed: September 12, 1980
    Date of Patent: October 19, 1982
    Assignee: International Business Machines Corp.
    Inventors: James R. Gardiner, William A. Pliskin, Martin Revitz, Joseph F. Shepard
  • Patent number: 4341009
    Abstract: A buried electrical contact is made to a substrate of monocrystalline silicon through a relatively thin layer of silicon dioxide without causing damage to the relatively thin layer of silicon dioxide. This is accomplished through depositing a thin layer of polycrystalline silicon over the relatively thin layer of silicon dioxide prior to forming the opening in the relatively thin layer of silicon dioxide for the electrical contact to the substrate. After the thin layer of polycrystalline silicon is deposited, an opening is formed therein so that the thin layer of polycrystalline silicon functions as a mask to etch a corresponding opening in the relatively thin layer of silicon dioxide. Then, a layer of polycrystalline silicon is deposited over the exposed surface of the substrate and the thin layer of polycrystalline silicon to form the electrical contact through the opening in the relatively thin layer of silicon dioxide to the substrate.
    Type: Grant
    Filed: December 5, 1980
    Date of Patent: July 27, 1982
    Assignee: International Business Machines Corporation
    Inventors: Robert F. Bartholomew, Paul L. Garbarino, James R. Gardiner, Martin Revitz, Joseph F. Shepard
  • Patent number: 4249968
    Abstract: A method of making a metal-oxide-semiconductor device is disclosed. A thin silicon dioxide insulating layer is formed on the surface of a planar silicon wafer. A first layer of intrinsic polycrystalline silicon is deposited over the dioxide layer, and a second layer of doped polycrystalline silicon is deposited over the intrinsic layer, thereby forming the gate. Subsequent hot processing steps result in diffusion of a portion of the dopant from the doped polycrystalline layer into and throughout the intrinsic layer so as to dope the latter. A metal contact layer is then deposited onto the gate and in superimposed vertical alignment with respect to the thin silicon dioxide insulating layer. The instrinsic nature of the first polycrystalline layer reduces grain growth and void formation in the polycrystalline silicon and thereby prevents the silicon dioxide from being attacked by hydrofluoric acid seeping through voids in the polycrystalline layer during subsequent processing.
    Type: Grant
    Filed: December 29, 1978
    Date of Patent: February 10, 1981
    Assignee: International Business Machines Corporation
    Inventors: James R. Gardiner, William A. Pliskin, Martin Revitz, Joseph F. Shepard